(Invited) An Investigation of the InGaAs MOS System for Future High Mobility Channel Applications

Wednesday, October 14, 2015: 15:10
103-B (Phoenix Convention Center)
P. K. Hurley, Y. Gomeniuk, J. Lin, S. Monaghan, I. M. Povey, M. E. Pemble, B. J. Hutchinson (Tyndall National Institute), B. Sheehan (Tyndall National Institute), V. Djara (IBM Zurich Research Laboratory), E. O'Connor (IBM Zurich Research Laboratory), and K. Cherkaoui (Tyndall National Institute, University College Cork)
As silicon devices reach the limit of dimensional scaling there is a growing interest in the use of high electron mobility channels, such as InxGa1-xAs, in conjunction high dielectric constant (high-k) gate oxides for n-channel Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) in FinFET structures [1] and in 3D integration schemes [2]. The understanding and control of electrically active defect states at the high-k/InxGa1-xAs interface and of charges within the atomic layer deposited (ALD) high-k films will be essential for the successful implementation of high mobility channel materials in MOSFET or tunnel FET configurations. The objective of this presentation will be to provide an overview of the current understanding of the density and distribution of electrically active defects at the high-k/InGaAs interface and of defect states located in the interfacial oxide transition region which are manifest as accumulation frequency dispersion and capacitance-voltage hysteresis. The presentation will focus on InGaAs with a 53% Indium concentration. The electrically active interface state density distribution is determined from fully fabricated InGaAs MOSFET structures based on the full gate capacitance in conjunction with the Maserjian Y-function and Poisson-Schrodinger simulations [3]. Comparisons to simulations will be discussed in terms of identifying potential candidates for the physical origin of the interface defects. Very significant progress has been made in recent years in the passivation and intrinsic elimination of high-k/In0.53Ga0.47As interface defects to the point where genuine surface inversion for n and p type InGaAs MOS structures can be achieved and this research will be reviewed [4]. The characteristic signatures of capacitance and conductance, which indicate genuine surface inversion for an InGaAs MOS structure in inversion, will also be discussed [5].

While significant attention has been focussed on interface states and fixed charges in the InGaAs MOS system, the issue capacitance-voltage (CV) hysteresis has received relatively little attention to date [4]. This is now becoming a more pressing issue as progress is being made in controlling interface defect levels. Results will be presented covering CV hysteresis for the HfO2/InGaAs and Al2O3/InGaAs MOS structures with a range of high-k oxide thicknesses. The experimental results indicate that the defect states responsible for the hysteresis are located in the oxide transition region near the InGaAs/high-k interface and that engineering of this interface region, which contains native oxides of In, Ga and As, is the key to the control of CV hysteresis and accumulation frequency dispersion [7].  Finally, the presentation will cover the application of CV analysis to the understanding and quantification of charged defect components for InGaAs on insulator structures for 3D integration [8]. 

The authors acknowledge the financial support of Science Foundation Ireland through the INVENT project (SFI/09/IN.1/I2633) and the EU through the project COMPOSE3 (FP7-ICT- 2013-11-619325).

[1] M. Radosavljevic et al., Tech.Dig.-Int. Electron Devices Meet, 126 (2010)

[2] L. Czornomaz, et al., Tech.Dig.-Int. Electron Devices Meet. 6479088, (2012)

[3] V. Djara, et al., Microelectronic Engineering 109 182–188 (2013)

[4] N. Goel, D. et al., Tech. Dig. - Int. Electron Devices Meet. 363, (2008)

[5] É. O’Connor, et al., Appl. Phys Lett 99, 212901 (2011)

[6] Scott Monaghan, et al., IEEE Transaction on Electron Devices,  61, 4176 (2014)

[7] Jun Lin, et al., J. Appl. Phys. 114, 144105 (2013)

[8] K. Cherkaoui et al., Microelectronic Engineering 147 63–66 (2015)