Increase in Oxide Trap Density Due to the Implementation of High-k and Al2O3 Cap Layers in Thick-Oxide Input-Output Transistors for DRAM Applications

Wednesday, October 14, 2015: 14:00
103-B (Phoenix Convention Center)
E. Simoen (imec), R. Ritzenthaler, M. J. Cho (Imec), T. Schram (Imec), N. Horiguchi (imec), M. Aoulaiche, A. Spessot (Micron Technology Belgium), P. Fazan (Micron Technology Belgium), and C. Claeys (Imec)
Work function engineering by the introduction of cap layers in a high-k gate stack  [1],[2] can be successfully implemented in logic and DRAM peripheral MOSFETs. In the latter case, a so-called Diffusion and Gate Replacement (D&GR) integration scheme has recently been proposed [3], whereby an Al2O3 cap is implemented for tuning the threshold voltage of the p-channel transistors. A key step is the diffusion anneal to form a dipole layer at the SiO2/HfO2 interface [1],[2], which is typically carried out in the range of 600 oC to 900 oC [3]. In addition to the peripheral transistors, also input/output (I/O) devices with a larger gate oxide thickness need to be fabricated in a DRAM chip as well. These may undergo also the HfO2 and Al2O3 deposition and subsequent thermal budget. The question addressed in this work is whether the large Equivalent Oxide Thickness (EOT) devices suffer from these additional processing steps, from a viewpoint of gate oxide quality and reliability. To that aim, low-frequency (LF) noise is used as a tool to probe the border trap profile in the thick oxide gate stack [4],[5]. Evidence will be given for the in-diffusion of Hf and Al in the thick SiO2 up to the silicon interface, giving rise to a strong increase of the oxide trap density and hence the 1/f noise Power Spectral Density (PSD).

            P-channel transistors have been processed on 300 mm wafers following the conditions of Table 1, with 5 nm SiO2 + polysilicon gate as a reference. The Al2O3 cap is deposited on top of the gate stack. LF noise measurements have been performed on 1 mm×0.170 mm area devices in linear operation (drain-to-source voltage VDS=-0.05 V) with the gate voltage VGS stepped from weak to strong inversion. As shown in Fig. 1, the spectra are typically 1/f-like, with occasionally excess Lorentzian noise components. It is also clear, however, that the frequency exponent is not constant in the studied frequency range from 3 Hz to 100 kHz. It will be shown that the 1/f noise is due to number fluctuations, i.e., is caused by trapping in the gate oxide. From Fig. 2, one can derive that the average input-referred voltage noise PSD (<SVG>) at 10 Hz (Fig. 2a) or 10 kHz (Fig. 2b) strongly depends on the process conditions, with the reference wafer showing at least one decade lower values. Using the formulas in Fig. 3, on can convert the 1/f spectra into an oxide trap density profile, showing a strong increase as soon as a high-k layer is present. The increase in trap density points to an in-diffusion of Hf and Al down to the Si/SiO2 interface, while the reference trap densities are typical for SiO2. It will, finally, be shown that there exists a good agreement between the trend in the oxide trap density derived from 1/f noise spectra and the Negative Bias Temperature Instability (NBTI) of similar p-channel devices. It is clear that for optimizing the quality and reliability of I/O transistors, one should suppress this in-diffusion.


[1] J. Robertson, J. Vac. Sci. Technol. B, 27, p. 277 (2009).

[2] A. Toriumi and T. Nabatame. ECS Trans., 25 (6), 3 (2009).

[3] R. Ritzenthaler et al., in IEDM Tech. Dig., The IEEE (New York) (2014).

[4] M. Aoulaiche et al., in Proc. ESSDERC, The IEEE (New York) (2013).

[5] E. Simoen et al., Semicond, Sci. Technol., 29, p. 115015 (2014).