Characterization of Low-Dielectric Constant Silicon Carbonitride (SiCN) Dielectric Films for Charge Trapping Nonvolatile Memories

The MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure with a silicon nitride charge trapping layer has received considerable attention for ultra-high density NVM technology. In this architecture, the trapped charge carriers in the charge trapping layer causes a shift in the threshold voltage of memory transistors. However, it is a critical challenge for MONOS-type NVMs to fulfill the requirements of fast programming and erasing speeds and long retention time simultaneously.

Recently, we have proposed the application of silicon carbonitride (SiCN) dielectric films with a low-dielectric constant (low-k) to the charge trapping layers [1-6]. The relative dielectric constant of SiCN films is 4.8-4.9, which is lower than that of silicon nitride films (~7). The carrier density in the charge trapping layer which is necessary to induce a fixed threshold voltage shift is a function of the dielectric constant of the charge trapping layer. The necessary carrier density in the SiCN charge trapping layer is low as compared to that in the silicon nitride charge trapping layer. This would result in low power consumption and high programming and erasing speeds in the SiCN-based memory. In the present study, we investigated the charge retention behavior of memory capacitors with the SiCN charge trapping layer and proposed a simple method for analyzing the trap distribution in the SiCN layer.

Memory capacitors with blocking oxide-SiCN-tunneling oxide stacked films were fabricated on the silicon substrates. A tunnel oxide film of 2.4 nm in thickness was first formed on p-type (100) silicon substrates using a rapid thermal oxidation technique. A 31.5-nm-thick SiCN film with a relative dielectric constant of 4.8-4.9 was grown at 400 °C using a PECVD technique. A 17.3-nm-thick blocking oxide film was grown using a PECVD technique. Finally, an aluminum film was deposited to form the gate electrode on the SiO_X-SiCN-SiO₂stacked films. Programming and erasing voltages of +14.3 V and -15.1 V were applied to the gate electrode with grounded the silicon substrate to inject electrons and holes from the substrate into the SiCN layer. Charge retention characteristics of the SiCN memory capacitors in the programming condition were measured at temperatures ranging from room temperature to 235°C. Many trap states were filled by electrons during programming operation. After programming operation and the successive baking at different temperatures, the flat-band voltage in the capacitors was shifted. This shift in the flat-band voltage is mostly due to the emission of trapped electrons from the SiCN layer.

Figure 1 shows the charge retention characteristics of the SiCN memory capacitors for four different temperatures. The occupancy function f is defined as the ratio of the density of filled trap states at any retention time t to the density of filled trap states at t=0 s. f was obtained from the flat-band voltage shift. We can see that the emission rates of electrons is thermally activated. Here, assuming that the electron emission is dominated by thermal excitation at higher temperatures, we have calculated the energy distribution of the trapped electrons. As shown in Fig. 2, the energy range of trapped electrons is obtained to be from 1.5 eV to 2.0 eV below the conduction band edge in the SiCN band gap.

The results show that the long-term data retention of the SiCN memory capacitor attributed to the presence of energetically deep traps in the SiCN band gap. Hence, the SiCN dielectric films with a low-dielectric constant can be employed as the charge trapping layer of the nonvolatile memories.

Acknowledgement:　We would like to express gratitude to S. Tanaka, H. Shibayama and J. Nakamura for their valuable discussions. This work was partly supported by a Grant-in-Aid for Scientific Research (No. 26420280) from JSPS.

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