(Invited) Threshold Voltage Stability Comparison of Commercial SiC Mosfets and Related Issues

Tuesday, October 13, 2015: 11:30
Ellis East (Hyatt Regency)
R. Green, A. Lelis (U.S. Army Research Laboratory), and D. Habersat (US Army Research Laboratory)
Silicon-Carbide (SiC) MOSFETs are beginning to gain wide acceptance for power electronics applications requiring high efficiency and high operational temperatures. There is a growing number of commercial offerings at 1200 V from different manufacturers that may have very distinctive processes that need to be evaluated in a consistent manner to make valid comparisons. As SiC MOSFET technology continues to mature, device performance and reliability should also improve. In recent years, a diverse number of publications in the literature have addressed the poor quality of the MOS gate dielectric layer, and the challenges related to charging of both interface defects and near-interfacial oxide defects during electrical and thermal stressing. A significant number of intrinsic defects in the gate oxide result from growth of the dielectric layer itself. Subsequent process steps can activate a number of these defects which can trap charge during electrical gate-stress, thereby altering the device threshold voltage. During bias temperature stressing, activation of additional oxide defects can occur, which gives rise to larger threshold voltage instabilities. The stability of the MOS threshold voltage under electrical gate-stress at high temperature is an important reliability phenomenon with potential application relevance. A large positive shift reduces on-state conduction, increases power losses, and may reduce efficiency in switch-mode converter applications. A large negative shift in the threshold voltage is a more serious reliability concern because of excessive drain leakage current in the MOS-channel during the off-state. This effect will limit blocking capability and possibly lead to device failure.

This work will provide an overview of threshold voltage stability issues in commercially-available SiC MOSFETs subject to both positive and negative gate-stress at high temperature. Figure 1 is a plot of the subthreshold-voltage shift as a function of unipolar (positive) bias stress time for commercial devices purchased between 2012 and 2015. Recent devices show significant improvement in threshold voltage shift for a +25 V gate-bias stress at 175 °C. The older commercial devices shift considerably more, with the onset of degradation occurring much earlier in time. We have also observed differences in the responses of devices from different manufactures for similar stress and test conditions.  It is expected that process differences among device manufacturers would in turn, result in differences in the bias-temperature-stress responses. A fuller discussion of these test results and related issues will be presented in the final paper.