(Invited) Reliability and Pulsed I-V Analysis of Vertically-Scaled GaN MIS-Hemts

Wednesday, October 14, 2015: 12:00
Ellis East (Hyatt Regency)
D. J. Meyer, B. P. Downey, J. A. Roussos, D. S. Katzer (U.S. Naval Research Laboratory), M. G. Ancona (U.S. Naval Research Laboratory), M. Pan (IQE RF LLC), and X. Gao (IQE RF LLC)
GaN solid-state power amplifiers are becoming more frequently utilized in RF applications due to their significant power density advantages over conventional III-V semiconductor materials.  Development of the core transistor technology, GaN high-electron-mobility transistors (HEMTs), has been the research focus of numerous groups around the globe.  One of the most recent thrusts in the community has been to extend the frequency performance of GaN HEMTs to the millimeter wavelength (MMW) range of 30 – 300 GHz.  To obtain power gain at these frequencies, device and heterostructure dimensions must be scaled down to minimize electron transit delay.  However, this scaling raises the peak electric fields in the device to extremely high levels and often limits the operational voltage range due to excessive leakage current related breakdown.  Historical solutions for managing peak electric fields, such as the use of source-connected field plates in microwave HEMTs, are generally avoided due to the excessive parasitic capacitance introduced.  Without field-plate management of peak fields, a critical question that remains to be answered is how to achieve reliable high power operation in a MMW GaN device. 

In our laboratory we have been exploring methods to simultaneously achieve high power gain at MMW frequencies along with high breakdown voltage [1, 2].  This talk will discuss an initial study that has investigated the effect of SiN gate insulator thickness on MMW GaN HEMT reliability.  As illustrated in Fig. 1, the heterostructure used in this work consists of an ultra-thin 2.3 nm In0.17Al0.83N / 1 nm AlN barrier, GaN channel and buffer layers grown on SiC by metalorganic chemical vapor deposition.  After heterostructure growth, molecular beam epitaxy was used to deposit 1, 3, 5, or 6 nm of SiN gate insulator at 575 °C.  Metal-insulator-semiconductor (MIS) HEMTs with 120 nm gate length were then fabricated using standard processing procedures described previously [2].  For the 5 nm SiN sample, an SF6 plasma recess etch was performed prior to gate metallization, creating a Schottky gate variant as a reference device.

After initial dc, pulsed, and RF electrical testing, devices from each sample were biased in class AB at VDS = 20 V on a Maury on-wafer load-pull system that had been tuned to achieve maximum output power.  To perform RF operation life testing (RFOL), large signal input power at 40 GHz was set to achieve peak power-added-efficiency while output power (Pout) and drain current were monitored as a function of time.  Fig. 2 shows the change in Pout over time for pairs of samples with different gate insulator thickness.  Interestingly, samples with thicker SiN showed less degradation in Pout relative to initial values.  The dc characteristics of the 6 nm SiN sample before and after stress are shown in Fig. 3.  This talk will discuss the measured results and implications for future MMW GaN HEMT design.

Acknowledgements:  The authors thank N. Green for his assistance with device fabrication.  This work was supported by the Office of Naval Research (P. Maki).


[1]           B. P. Downey et al., "Effect of SiNx gate insulator thickness on electrical properties of SiNx/In0.17Al0.83N/AlN/GaN MIS–HEMTs," Solid-State Electronics, vol. 106, no. pp. 12-17, 2015.

[2]           B. P. Downey et al., "SiNx/InAlN/AlN/GaN MIS-HEMTs With 10.8 THz V Johnson Figure of Merit," IEEE Electron Device Lett., vol. 35, no. 5, pp. 527-529, 2014.