827
(Invited) Variability in FinFET SRAM Cells
(Invited) Variability in FinFET SRAM Cells
Tuesday, October 13, 2015: 10:00
105-B (Phoenix Convention Center)
Recently, variability of the devices due to the various random sources is increasing and will reduce the yield of the circuit. To overcome these problems, FinFET device technologies have been proposed and investigated for many years. They have an intrinsic strength against the SCE and they allow the use of intrinsic channel and thus reduce the random dopant fluctuation.
However, variability of the FinFET still remains. Variations are caused by fluctuations of the gate-length (ΔLG), the fin-width (ΔTFin), the oxide thickness (ΔTox), the line edge roughness of fin and gate electrodes. In addition to these variations, a new source of variation is generated through an introduction of the metal gate (MG) due to the dependency of the work function (WF) on the orientation of metal grains.
To understand the origin of the Vth variation in the MG FinFET, we experimentally evaluate the effect of the ΔLG, ΔTFin, and ΔTox to the Vth variation by measuring the standard deviation of these values. The standard deviations of the dimension variation sources such as the ΔLG and ΔTFin were measured by counting the statistical distribution of the size using a scanning electron microscope (SEM). The same chip is used after the electrical measurements. The ΔTox variation was measured by ellipsometry using (110) oriented test wafers which have the same orientation with the side-wall channel of the FinFET. It is revealed that the ΔLG, ΔTFin, and ΔTox contributions to the Vth variation are insignificant since their standard deviations and partial derivatives are small. Thus, it is concluded that the main variation source of the TiN MG FinFET is the work function variation (WFV) of the TiN. The observed deviation of 30 mV is almost the same value with the previous reports. The possible explanation of the WFV is an over 200 mV work function difference between (100) and (111) oriented grains of TiN and there is also an additional WFV due to the composition or nitrogen concentration of the TiN. Moreover, we have developed and introduced amorphous metal gate into FinFET for the first time using the TaSiN metal gate to overcome the work function variation in the metal gate. The TaSiN gates exhibit smaller variability than that of TiN and the record smallest variability is realized.
The Vth variation will directly cause the variation in the SRAM performance. To overcome the variation problem, we have developed independent doubl-gate (IDG) FinFET SRAM technologies. We have developped two types of FinFET SRAM cells using the IDG-FinFET. One is a flexible-Vth (Flex-Vth) SRAM cell and the other is a flexible pass-gate (Flex-PG) SRAM cell. In the Flex-Vth cell, all the transistors in the cell are composed by the IDG-FinFET. The Vth of the all transistor can be controlled by the external bias to the Vth-control-gate. The real values of Vth can be tuned keeping the symmetry of Vth. Thus, the stand-by leakage current and the short circuit current of the cell are dynamically controlled. For the Flex-PG cell, IDG-FinFETs are used only for the PG and the other transistors are composed by the common-DG FinFET. The Ion ratio of the pull down to the pass gate which corresponds to the β-ratio is thus flexibly changed. A great enhancement of the read margin is experimentally confirmed for the Flex-PG cell. Moreover, significant reduction of the variation in the SRAM characteristics is clearly demonstrated. Finally, scalability of the Flex-PG SRAM technology is evaluated by the compact model analysis. Device parameters including variations are satisfactory to the ITRS roadmap. The result shows that the TaSiN gate and the Flex-PG technology enable 12.5-nm-LG SRAM with the sufficient static noise margin.
However, variability of the FinFET still remains. Variations are caused by fluctuations of the gate-length (ΔLG), the fin-width (ΔTFin), the oxide thickness (ΔTox), the line edge roughness of fin and gate electrodes. In addition to these variations, a new source of variation is generated through an introduction of the metal gate (MG) due to the dependency of the work function (WF) on the orientation of metal grains.
To understand the origin of the Vth variation in the MG FinFET, we experimentally evaluate the effect of the ΔLG, ΔTFin, and ΔTox to the Vth variation by measuring the standard deviation of these values. The standard deviations of the dimension variation sources such as the ΔLG and ΔTFin were measured by counting the statistical distribution of the size using a scanning electron microscope (SEM). The same chip is used after the electrical measurements. The ΔTox variation was measured by ellipsometry using (110) oriented test wafers which have the same orientation with the side-wall channel of the FinFET. It is revealed that the ΔLG, ΔTFin, and ΔTox contributions to the Vth variation are insignificant since their standard deviations and partial derivatives are small. Thus, it is concluded that the main variation source of the TiN MG FinFET is the work function variation (WFV) of the TiN. The observed deviation of 30 mV is almost the same value with the previous reports. The possible explanation of the WFV is an over 200 mV work function difference between (100) and (111) oriented grains of TiN and there is also an additional WFV due to the composition or nitrogen concentration of the TiN. Moreover, we have developed and introduced amorphous metal gate into FinFET for the first time using the TaSiN metal gate to overcome the work function variation in the metal gate. The TaSiN gates exhibit smaller variability than that of TiN and the record smallest variability is realized.
The Vth variation will directly cause the variation in the SRAM performance. To overcome the variation problem, we have developed independent doubl-gate (IDG) FinFET SRAM technologies. We have developped two types of FinFET SRAM cells using the IDG-FinFET. One is a flexible-Vth (Flex-Vth) SRAM cell and the other is a flexible pass-gate (Flex-PG) SRAM cell. In the Flex-Vth cell, all the transistors in the cell are composed by the IDG-FinFET. The Vth of the all transistor can be controlled by the external bias to the Vth-control-gate. The real values of Vth can be tuned keeping the symmetry of Vth. Thus, the stand-by leakage current and the short circuit current of the cell are dynamically controlled. For the Flex-PG cell, IDG-FinFETs are used only for the PG and the other transistors are composed by the common-DG FinFET. The Ion ratio of the pull down to the pass gate which corresponds to the β-ratio is thus flexibly changed. A great enhancement of the read margin is experimentally confirmed for the Flex-PG cell. Moreover, significant reduction of the variation in the SRAM characteristics is clearly demonstrated. Finally, scalability of the Flex-PG SRAM technology is evaluated by the compact model analysis. Device parameters including variations are satisfactory to the ITRS roadmap. The result shows that the TaSiN gate and the Flex-PG technology enable 12.5-nm-LG SRAM with the sufficient static noise margin.