(Invited) Enabling SiC Yield and Reliability through Epitaxy and Characterization

Monday, October 12, 2015: 14:00
Ellis East (Hyatt Regency)
H. Das, S. Sunkari, M. Domeij, A. Konstantinov, F. Allerstam (Fairchild Semiconductor), and T. Neyer (Fairchild Semiconductor)
Silicon Carbide offers a compelling alternative for power devices. Its multiple uses in power efficient applications have led to a rush in commercialization of various device families. The major issues facing widespread adoption of SiC devices are cost and reliability. There are many facets to achieving and meeting consumer expectations in both these areas. One important part of reducing cost is moving to larger diameter substrates. This is currently challenging due to the lack of sufficient quality in 150mm wafers compared to 100mm wafers. Though quite some progress has been made on 150mm substrates, they still have a much larger number of crystal defects and macro defects than mature 100mm substrates. This leads to more concerns regarding reliability issues related to crystal defects in the substrates and subsequently in the epitaxial layers. This work focuses on ways of mitigating reliability issues while still leveraging the use of 150mm material.

One facet of the reliability is dealing with defects that can cause bipolar degradation after stress [1,2]. These affect not just bipolar switches like BJTs but also the body diode of the MOSFETs. There are many approaches like buffer layers, pre-treatments, growth interrupts etc. to reduce these defects in the epi and prevent their propagation into the active layers. However some defects do make it through to the active layers. Traditional methods of detecting these defects like Basal Plane Dislocations (BPDs) are destructive in nature like molten KOH etching. Even this method is lacking since it only exposes the defects that break the surface of the epitaxial layers. Many of these BPDs can get converted to threading edge dislocations in the active regions and are therefore never detected by KOH etching. Recently many groups have started using Infra-Red Photoluminescence (IR PL) (700nm+) to detect both the basal plane dislocations and stacking faults [3-5] utilizing full wafer scans. In one of our previous works [6], we have used a similar method to screen out die that would exhibit degradation under forward bias stress. There are however some cases where the detection and screening using this method becomes challenging. This happens when the defects propagate in the buffer layer to just below or just into the active layer. This is because there is a lack of PL signal from the typically high doped buffer layers. This results in no signal or extremely faint PL signals coming from the buffer layers. As other research groups [7] have shown these defects in the buffer near the interface, have the tendency to expand into the active regions as a result of carrier recombination, thus killing or degrading the device performance.

The solution to this problem is using the Near Ultra Violet PL spectrum to detect the crystal defects in the SiC material. The defects are detected as an absence of bandgap recombination spectra and thus detect any defects that cause non-radiative recombination. The BPDs are clearly detected even in highly doped buffer regions with sufficient SNR along with brighter features of the BPDs in the active layers. This stronger signal along with the longer overall length enables automated detection, classification and screening of the required defect types and provides visibility into the conversion efficiency of the buffer layers. This gives a very fast feedback path for epitaxial development to reduce the presence of these defects in the active regions. Traditionally a thorough feedback loop would involve fabricating and stressing PN diodes on the epi, which takes multiple weeks [6]. Other types of crystal defects like grain boundaries that are more prevalent in less mature 150mm substrates can also be detected using this method. This enables the identification of defective regions and defective wafer batches, thereby providing a fast and non-destructive feedback loop to the substrate vendors. A combination of these methods enables the confident use of 150mm substrates while maintaining the reliability expectations of the device customers. Results from improved quality epitaxial layers on both 100mm and 150mm substrates will be presented. Comparison and validation of the defect scan data to molten KOH etching will also be presented.  

[1] A. Agarwal et al. Mater. Sci. Forum, 527-529, pp1409-1412 (2006)

[2] L. Farese et al. Mater. Sci. Forum, 645-648, pp1037-1040 (2010)

[3] T. Tanaka et al. Mater. Sci. Forum, 778-780, pp91-94 (2014)

[4] M. Odawara et al. Mater. Sci. Forum, 778-780, pp382-385 (2014)

[5] S. Yamamoto et al. Mater. Sci. Forum, 778-780, pp951-954 (2014)

[6] B. Buono et al. Mater. Sci. Forum, 778-780, pp1017-1020 (2014)

[7] N. A. Mahadik et al. Appl. Phys. Lett. 100, 042102 (2012)