(Invited) Ion Implantation into GaN and Implanted GaN Power Transistors
We have previously demonstrated Si ion implantation for GaN HEMTs  and MESFETs  to reduce the contact resistance and fabricate a lightly-doped channel region. In addition, we have recently demonstrated normally-off GaN MISFETs with Si ion implantation into p-type GaN  and N ion implantation for the device isolation . Si implanted MISFETs have achieved the high threshold voltage (Vth) of +3.4 V . Moreover, we have succeeded to fabricate selective p-GaN regions with Mg ion implantation and this result made it possible to control the Vth of GaN MISFETs from -5 V to +1.5 V. These results indicate a definite availability for power switching device applications.
As known well, it is very difficult to form a p-type conductive layer with ion implantation on GaN. The GaN-based devices are usually fabricated on either a sapphire substrate or a Si substrate with a large diameter and at low cost. However these substrates cause many defects in GaN due to large lattice mismatch between epitaxial layers and the substrate. Such defects of high threading dislocation density over 109 /cm2 cause substantial current leakage and such layers would be deteriorated by the high temperature annealing for activation of the implanted Mg and create donor-like defects which compensates the Mg acceptors.
P-type conversion by Mg ion implantation was attempted using high quality n--GaN epitaxial layer grown on a free-standing GaN substrate. Low temperature PL spectra showed Mg-acceptor related emissions. Vertical diodes showed clear rectifying I-V characteristics. UV and blue-green light emission was observed at forward biased condition. Positive Hall coefficients were observed by van der Pauw measurements. These results indicate the p-type conversion was possible using high quality GaN layers grown on free-standing GaN substrates, which can lead new device structures and processing for future GaN power devices.
 B.R. Park, et al., Semisonductor Science and technology, Vol. 28, No. 12, (2013)
 E. Suekawa, et al., Proceeding of ISPSD & ICs, 11.12, 249 – 252 (1998)
 S.H. Ryu, et al., IEEE Electron Device Letters, Vol. 22, No. 3, 124 – 126, March (2001)
 K.W. Chu, et al., IEEE Electron Device Letters, Vol. 34, No. 2, 286 – 288, February (2013)
 K.Nomoto, T. Nakamura, et al., IEEE Electron Device Letters, Vol. 28, No. 11, 939 – 941, November (2007)
 K.Nomoto, T. Nakamura, et al., Proceeding of MRS Fall Meeting, Vol. 892 (2005)
 S. Gu, K. Nomoto, T. Nakamura, et al., physica status solidi (c), Vol. 10, Issue. 5, 820 – 823, May (2013)
 H. Kasai, T. Nakamura, et al., physica status solidi (c), Vol. 11, Issue. 3-4, 914 – 917, April (2014)
 S. Taguchi, K. Nomoto, T. Nakamura, et al., physica status solidi (c), Vol. 9, Issue. 3-4, 858 – 860, March (2012)