Triple-gate finFET manufacturing implementation has been successfully enabling continuance of CMOS scaling and Moore’s law [1], but it faces increased scaling challenges for sub-10nm nodes. Gate-all-around (GAA) nanowire (NW) FETs with the thin-body of the device, in a lateral or vertical configuration, fully wrapped around by the gate can be considered the ultimate scaling limit of finFETs [2-4]. They have the potential to offer superior short-channel electrostatics, and are thus regarded as one of the most promising candidates to further support the CMOS roadmap. In this work, we report a comprehensive evaluation of these two different device architectures from a device and circuit perspective, focusing on the key topics of gate stack integrity, leakage, reliability and noise performance and on the impact of the process options used. For simplicity, all devices were built on SOI substrates, with GAA lateral NWFETs obtained via a fins release process at replacement metal gate (RMG) module, which is high density compatible, and wherein diluted-HF was used to remove the BOX under the fins in areas previously covered by the dummy-gates [while the rest of the wafer is covered by the inter-layer dielectric level-zero oxide (ILD0)]. The gate stack used consists of: interfacial layer (IL)-SiO₂/HfO₂ followed by the effective work function (EWF)-metal (TiN or a TiAl-based stack) and W fill-metal. Examples of TEM images taken across a wire (GAA-NWFET) or a fin (triple-gate finFET) after full processing are shown in Fig.1 [4].

Intrinsic transistor performance (ITP) characteristics show that GAA-NWFETs clearly outperform finFETs when normalizing I_ON-I_OFF per footprint. Furthermore, an evaluation of several doping strategies for both type of devices, using ion implantation (I/I), allowed a comparison of inversion-mode (IM) FETs built with conventional junctions or an extensionless (Extless) scheme [4,5] vs. junctionless (JL) transistors [4,6]. To note that the latter are particularly advantageous in their process simplicity (no junction formation requirements) and compatibility with lower thermal budget flows. Reliability wise, optimized JL and Extless can be very attractive options thanks to a lower oxide field (E_ox) at operating conditions. This is indeed confirmed by the GAA-NWFETs in Fig.2. Control of the lateral BOX recess during the fins release process in the GAA flow, and hence of the lateral bottom-gate overlap, is important not only for parasitic reasons but also for reliability purposes. Indeed, TCAD predicts a higher E_ox at the bottom-gate edges in case of excessive lateral BOX recess which can lead to degraded BTI behavior for GAA-NWFET vs. finFET. The impact is however considerably less for Extless and JL, increasing the robustness of these devices against process variations in the lateral BOX recess. JL devices were also seen to have improved on and off state hot carrier (HC) reliability behavior as compared to other IM GAA-NWFETs [7]. Interestingly, improved subthreshold slope (SS) values after HC stress were also measured in some JL GAA-NWFETs as a result of the improved electrostatic control and the generation and location of acceptor type of interface traps in the wires of slightly concave sidewalls shape. Low-frequency (LF) noise analysis results suggest to a first order no significant impact of the device architecture on the gate stack integrity in regards to traps/defects. In addition, in agreement with BTI and HC results, JL GAA-NWFETs also show reduced noise. These characteristics, together with the devices smaller I_OFF values yielding ring oscillators with substantially lower power dissipation, indicate JL can be an attractive option for low power circuits. Improvements in noise, reliability and mobility performance were also obtained in GAA-NWFETs by introduction of a TiAl-based EWF-metal [4,8], in line with the results previously reported in [9] on finFETs using Al diffusion mechanisms for EWF modulation.

References

[1] S. Natarajan et al., IEDM Tech. Dig., p.71 (2014);

[2] S. Bangsaruntip et al., IEDM Tech. Dig., p.526 (2013);

[3] S.-G. Hur et al., IEDM Tech. Dig., p.649 (2013);

[4] A. Veloso et al., VLSI Tech. Dig., p.138 (2015);

[5] A. Veloso et al., SSDM Tech. Dig., p.789 (2012);

[6] J.-P. Colinge et al., Nature Nano., p.225 (2010);

[7] M. J. Cho et al., IEDM Tech. Dig., p.366 (2015);

[8] L.-Å. Ragnarsson et al., VLSI Tech. Dig., p.56 (2014);

[9] A. Veloso et al., VLSI Tech. Dig., p.194 (2013).