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Lateral Non-Uniformity Reduction by Compensatory Metal Embedded in MOS Structure with Ultra-Thin Anodic Oxide

Monday, 30 May 2016: 14:30
Sapphire 410 A (Hilton San Diego Bayfront)
J. Y. Chen, W. C. Kao, and J. G. Hwu (National Taiwan University)
Lateral non-uniformity (LNU) of gate dielectric has been a serious problem in modern metal-oxide-semiconductor (MOS) devices [1], [2]. It was found the LNU became more severe after adopting the post-metalization annealing (PMA) due to possible spiking of metal. The interface of metal and gate dielectric was believed to be uneven after PMA. In this work, a method to ameliorate the lateral uniformity in MOS capacitors was proposed. By utilizing the anodic oxidation compensation technique to form a compensatory aluminum layer embedded in MOS structure, obvious improvement in lateral oxide uniformity was observed. The schematic of anodic oxidation compensation is shown in Fig. 1. Accordingly, two batches of MOS capacitors with ultra-thin anodic oxide with equivalent oxide thickness (EOT) ranging from 2 nm to 3.4 nm was prepared for comparison. One is denoted as MOS (MOS stands for the simple Al/SiO2/Si(p) structure), while the other one is denoted as EAMOS (EAMOS stands for Al/Al2O3/Al/SiO2/Si(p) structure with compensatory embedded aluminum).

From our previous work, it is known that the electrical characteristics of MOS capacitors in accumulation regime are area-dependent [3]. Hence, the electrical characteristics in accumulation regime are practical for examining the degree of LNU. Fig. 2 shows the current-voltage (I-V), current density-voltage (J-V) and capacitance per unit area-voltage (C’-V) characteristics of both devices. It is obvious that the area-dependence is applied much better in EAMOS devices, which clearly indicates the reduction of LNU. Furthermore, in order to verify the uniformity improvement in whole samples, the percentage dispersions of different device areas of current density and capacitance per unit area in accumulation regime with varied EOT’s are illustrated in Fig. 3. In Fig. 3, for each EOT, the quantity of dispersion of MOS devices is larger than the value of EAMOS devices. Fig. 3(a) shows that the average percentage dispersion of MOS devices for capacitance per unit area with various EOT’s is 3.95%, which is larger than the value of 2.28% of EAMOS devices. Fig. 3(b) shows that the average percentage dispersion of MOS devices for current density with various EOT’s is 90.33%, whereas the value of EAMOS devices (27.7%) is much smaller. These results further serve as the evidences of lessening of LNU.

In addition, the breakdown behaviors also point out the improvement in oxide uniformity. Fig. 4 shows the characteristics of time-zero dielectric breakdown (TZDB) of thirteen identical devices for both MOS and EAMOS samples. The values of breakdown voltage for EAMOS devices are more consistent (-4 V to -5 V), while the values for MOS devices range from -2.5 V to -5 V, which are comparatively divergent. Furthermore, currents at -2 V and -8 V are more congruous for EAMOS devices. Consequently, these results give another support to the improved oxide uniformity. Finally, benefited from the reduction of LNU, the lateral distribution of vertical electric field must be more uniform. So when biasing at inversion regime, we believed that the induced minority carriers would distributed more uniform in lateral direction. Therefore, the lateral electric field induced by the non-uniformity of minority carriers would be attenuated. So relieved from the disturbance of lateral Coulomb force, the response of minority carriers to the small signal of gate voltage is believed to be more significant in the EAMOS devices than the MOS devices. Fig. 5 shows the capacitance-voltage (C-V) characteristic of both MOS and EAMOS devices with EOT of 3.4 nm and various frequencies. It is obvious that the frequency response of inversion capacitance is more significant for the EAMOS device than the MOS device. This outcome is consistent with the explanation given above, and it is of use for the circuit design consideration in MOS-based devices.

This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. NSC 102-2221-E-002-183-MY3 and MOST 103-2622-E-002-031.

References

[1]   W. K. Chim and P. S. Lim, J. Appl. Phys., 91, 1304 (2002).

[2]   D. Z. Y. Ting, Appl. Phys. Lett., 75, 2769 (1998).

[3]   H. W. Lu and J. G. Hwu, ECS Trans., 58, 339 (2013).