Building nonvolatile memory directly into a CMOS low-k/Cu interconnects would reduce latency in connectivity constrained computational devices and reduce chip’s footprint by stacking memory on top of logic. In the relentless drive to lower the interconnect time delay, porous low-k dielectrics are being currently explored. In this paper, porous dielectrics are being electrically characterized and their suitability for resistive switching (RS) assessed. Metal-Insulator-Metal (MIM) structures have been manufactured with bottom Cu electrode and with top island-shaped W or Pt counter-electrode. The porous dielectric was a-SiC:H or a-SiOC:H with level of porosity varying between 8% to 25%. The thickness of the porous dielectric is 20 nm and the dielectric constant k varied between 3.1 (@ 8% porosity) and 2.5 (@25% porosity). Some devices have a 2 nm SiCN diffusion barrier (DB), either at the Cu or W/Pt electrode or at both electrodes. The SiCN layers serve a dual-purpose: i) to prevent Cu diffusion, and ii) to prevent Cu, W, and Pt protrusion into pores and voids of porous dielectrics. A bulk majority of devices has been found conductive from the beginning and less than 10% - only those with at least one DB - displayed RS behavior. The intrinsic conductive state has been found to scale with the area of the top island electrode, and its temperature coefficient of resistance (TCR) has been found to be TCR=0.0028 K^-1. Both findings are consistent with high concentration of Cu in the dielectric indicating bulk conduction. This means that porous dielectrics are vulnerable to metal diffusion and even two diffusion barriers of 2 nm are marginal in arresting Cu diffusion. When subjected to resistive switching, the intrinsic resistance R_int was found to be dependent on the applied compliance current I_cc. R_int decreases linearly with increasing I_cc when I_cc is smaller than a critical value I_cc(crit), typically 10 mA; for I_cc larger than I_cc(crit) R_int is constant. This finding is explained with improved ionization of copper and more homogenous Cu distribution through out the dielectric.

The RS behavior was tested in two modes: a) positive bias applied, and b) negative bias applied to Cu electrode, while W/Pt electrode are being grounded. At positive bias, a few samples displayed resistive behavior where a Cu filament could be formed, and subsequently reset and set several times. Thus, as a proof of concept, it has been demonstrated that resistive switching can be realized in porous dielectrics. It has been found that devices with W electrode showed superior behavior compared to Pt devices. Best resistive switching behavior was found with dielectric of 25% and with both SiCN barriers at Cu and at W electrode. The filament formation at positive and negative bias results in different type of a filament. Filaments formed at positive bias applied to Cu electrode are Cu filaments and filaments formed at negative bias are attributed to defects or broken bonds of the dielectric matrix. Measurements of temperature coefficient of resistance (TCR) have confirmed that both types of filaments have substantially different TCR coefficients. TCR of the filaments created at positive and negative bias has been measured and found to be 0.0031 K^-1 for positive and 0.0021 K^-1 for the negative bias, respectively. TCR=-0.0031K^-1 has been found to be characteristic of Cu filaments in Cu/TaO_x/Pt devices, and TCR=0.0021K^-1 is consistent with oxygen vacancy filaments in the same devices. Hence, filaments with 0.0031K^-1 have been identified with Cu filaments and filaments with 0.0021K^-1 with defect filaments. Those devices that have shown resistive switching were found to be sensitive to the level of I_cc. For I_cc<100 mA the on-state is volatile, i.e. the device reverts to the off-state when it is no longer powered. For I_cc>1 mA, the on-state was non-volatile. In many cases, the non-volatile state was a permanent one, i.e. the device could not be reset. Devices that were not conductive from the beginning were subjected to a 5 min anneal at 40 ^oC, 60 ^oC, and 100 ^oC. The electrical measurements confirm that with increasing temperature more and more samples became intrinsically conductive; at 100 ^oC all the samples (including those with two diffusion barriers) became intrinsically conductive. These results confirm that the devices suffer from excessive Cu diffusion at the manufacturing stage of the devices. Surprisingly, it has been also found that – for those devices that displayed resistive switching – the forming voltage increased with increasing level of porosity. The present study gives good insights and establishes a solid data base for further improvement of the implementation of porous dielectrics into CMOS BEOL.