Over the past decade traditional scaling by simple linear shrinking has effectively ceased as IC makers have adopted new 3-dimensional device structures, complex integration schemes and new processes and materials for an expanding number of applications in order to overcome fundamental physical limits. This trend will accelerate as devices are scaled to a level approaching atomic dimensions.  Dielectric materials with tailored properties are required to meet future device needs.  And deposition processes that are self-limited (e.g. Atomic Layer Deposition (ALD)), or self-directed (e.g. selective deposition) will enable those materials to be used in scaled 3D devices.  Highly tailored ALD processes are being investigated to fabricate functional material layers. Interspersed treatments and doping to make ternary materials may be used to modify the physical and electrical properties of ALD films further in order to optimize the resulting physical or electrical properties. To improve device contacts, ultra-thin dielectrics and metal layers may be deposited inside of high aspect ratio contact structures in order to provide lower contact resistivity- or may be used to provide solutions for integration of new contact structures. Selective deposition processes can be used to deposit functional materials only where they are needed, thus reducing the patterning burden during IC manufacturing. Future use of new transistor channel materials, such as III-V and Ge, will require the use of ALD gate dielectrics with compatible treatment schemes in order to passivate defects and provide EOT scaling inside of ultra-high ratio replacement gate structures.  Examples of these and similar processes will be described and discussed with the goal of discerning a path beyond 10nm devices.