With feature size of transistors reducing down to sub-20 nm nodes, high mobility channel materials and novel device structures are critical to further improve the performance of transistors. Junctionless nanowire transistor (JNT) is recently proposed and regarded as promising candidate structure due to its simple fabrication process and excellent electronic properties [1]. Germanium-on-insulator (GOI) substrate is regarded as promising substrate due to its advantages of both Ge and on-insulator substrates. Although GOI-based JNTs have been reported [2,3], the performances are far from satisfactory. In this work, we fabricated high performance GOI-based JNTs with much smaller dimensions, where channel length and width are both less than 100 nm, and demonstrated their fabrication process and electrical properties in detail.

Fig.1 shows SEM images of tri-gate JNTs with different dimension, (a)W/L=40nm/70nm and (b) W/L=40nm/100nm, respectively. Fig.2 shows TEM image of a GOI sample with T_ge=10 nm. The original thickness of Ge film was about 50 nm. We reduced T_ge down to 10 nm using a simple wet retching method as reported in our previous work [4]. Fig.3 shows the schematic diagrams of fabrication process. To reduce costs and improve efficiency, we used both optical lithography (OL) and electron beam lithography (EBL). First, we used OL to define active region of the devices. GeO₂ channel passivation was carried out by ozone oxidation at 300 °C for 30 min. Then EBL was carried out to define the channel and gate electrode, which had much smaller dimensions. Finally, we used OL and lift-off process to define measuring electrodes.

Fig.4 (a) shows I_d-V_g characteristics of JNTs with  T_ge =20nm and T_ge=10nm, respectively. It can be observed that I_on/I_off ratio of the JNT with T_ge=10nm is larger than 10⁵ at V_d= -1V. The subthreshold slope at V_d= -0.1V and the drain induced-barrier lowering (DIBL) are estimated to be 110 mV/dec and 140 mV/V, respectively. With decrease of T_ge, we get better device performance. Fig.4 (b) shows the I_d-V_d characteristics of JNT with W/L=40nm/70nm, N_a=10¹⁸ cm^-3 and T_ge=10nm. Liner and saturation regions are clearly exhibited. Fig.5 (a) shows the influence of temperature on I_d-V_g characteristics of JNTs with W/L=40nm/70nm, N_a=10¹⁸cm^-3 and T_ge =10nm. It can be observed that with increase of temperature leakage current increased dramatically. Fig.5 (b) shows mobility of the same JNT. The reported mobility values of a GOI JNT with N_a= 10¹⁹ cm⁻³ [2] and a conventional Si pMOSFET [5] are also plotted for comparison. The peak mobility is larger than 200 cm²V^-1S^-1, which is close to that of bulk germanium with a doping concentration of 10¹⁸ cm⁻³.

   In summary, we fabricated high performance GOI-based JNTs using a Si-compatible process which combines OL and EBL. Good I_on/I_off ratio, subthreshold slope, DIBL and mobility are extracted, which indicating that ultra-thin body GOI-based JNTs are promising for high performance circuits. The device performance can be improved by optimizing the fabrication process and device structure.

Acknowledgments: This work was supported in part by the National Natural Science Foundation of China (No. 61306105).

[1] J. P. Colinge et.al, Nat. Nanotechnol. 5, 225, 2010. [2] D. D. Zhao et al. Jpn. J. Appl. Phys., Part 1, 51, 04DA03, 2012. [3] R. Yu et al., Phys. Status Solidi RRL 8, 65, 2014. [4] C. Sun et al. ECS Solid State Lett. 4, P43, 2015. [5] S. Takagi et al, IEEE Trans. Electron Devices, 41,2363, 1994.