The introduction of high-k metal gate (HK/MG) stack has enabled the resumption of Moore’s Law at the 45/32nm nodes, when the conventional Poly/SiON gate stacks failed to meet the required scaled-down performance targets. Despite the well demonstrated benefits such as reduced gate leakage, HK/MG integration scheme itself brings about new challenges in Si-based semiconductor process technologies. Among them, the most critical and stringent step is RMG CMP, which is tasked to deliver gate height uniformity within the range of a few nanometers on all chips across the entire 300mm wafer for 14nm technology nodes and beyond.

Conventional approaches to CMP planarity and uniformity often include the optimization of carrier zone pressure, platen/carrier rotation, slurry flow, conditioning sweep profileetc. Advances in CMP equipment technologies have also enabled new possibility such as multi-zone carrier pressure control through APC for within-wafer non-uniformity (WiWNU) reduction. Another widely-adopted approach is to rely on the high-selectivity of slurries to “stop dead” on the final layer of interests (e.g., tungsten in the case of RMG) without creating excessive local topography due to oxide erosion. While all the above approaches prove effective to certain degree, they are, by nature, wafer-level to sub wafer-level processes. As a consequence, it is difficult for them to differentiate between dies locally, for example, and correct the non-uniformity accordingly to the range of a few nanometers.

In this contribution, an alternative planarization scheme for RMG is presented to enable nano-scale gate height uniformity control across all dies on 300mm wafers. The new scheme begins with conventional high-selectivity CMP process (pass-1 W-CMP) to remove overburden and polish the gate height down to a few nanometers thicker than the final target, followed by all-die gate height measurement on all wafers. Then the gate height data are fed forward to a GCIB tool, where location-specific process (LSP) takes place to trim the oxide down to a pre-determined target, die by die, through high-energy raster ion beam with high oxide-to-tungsten selectivity. This is followed by a final tungsten touch-up CMP process with high tungsten-to-oxide selectivity to level off the protruded metal patterns and drive the gate height to final target.

Applied to SOI-based deep-trench (DT) and FINFET integrated wafers based on 14nm ground rule, the new RMG planarization scheme above demonstrates supreme gate height uniformity. Gate height WiWNU reduces continuously from ~ 2.95% post pass-1 W-CMP to 1.85% post GCIB, and to 1.51% post T/U CMP. The 3sigma of gate height across all dies on 300mm wafers is less than 3nm. The underlying mechanism to achieve nano-scale planarity and uniformity control by this new planarization method will be discussed.