Wednesday, 1 June 2016: 13:10
Sapphire 411 B (Hilton San Diego Bayfront)
With semiconductor technologies driving towards sub 14nm nodes, FIN based field effect transistors (FINFETs) have been the preferred design to meet device power and performance requirements. At the core of FINFET transistor design is gate last/replacement metal gate (RMG) integration scheme due to the advantages in thermal budgets. Chemical mechanical planarization has evolved from planarization technique to technology enabler for this integration scheme. Replacement metal scheme has its own share of challenges- the integration scheme is quite complex. Chemical mechanical planarization (CMP) plays a key role in enabling this integration with various CMP steps supporting dummy poly gate formation, poly removal and replacement metal gate formation. The final gate height of the replacement metal gate is one of the most important parameters controlling device resistance. Even a change of 1nm gate height can result in overall variation of 5ohms/sq resistance. This requires CMP to control gate height as tightly as possible for every wafer. The two important factors contributing to the overall gate height variation are upstream processes and the metal gate CMP process itself. It is well known that CMP has its own variability in removal rate depending on consumable life resulting in unstable gate height. The gate height variation needs to be controlled within wafer and every wafer. A dedicated metrology tool connected to the polishing tool has been employed for many years to measure wafer thickness parameters. This onboard metrology tool is used to measure every wafer and the data is used to develop automated process control to improve overall within wafer and wafer to wafer variation. A two fold approach is used to achieve this. Integrated automated process control (iAPC) is initially used to control wafer to wafer variation and furthermore, zonal integration automated process control is used to improve within wafer uniformity. The basic concept is to use metrology data collected from each wafer and create a model to adjust polishing time to achieve desired final gate height target. Using these two approaches, gate height control of less than 5nm has been demonstrated consistently. Both these approaches will be discussed in detail.