With the introduction of tri-gate at 22nm technology node by Intel, other logic chip manufacturing technology developers have steadily migrated from planar to 3 dimensional FinFET technology at the fron-end-of-line. Historically, at 0.8μm technology node, there was no CMP although 2-3 metal levels were used. At 0.35μm technology node, a CMP step was introduced. CMP became mainstream with multiple steps requiring CMP at 90nm technology node which continued until 2x nm technology node.  However, at 1x (e.g. 14nm) technology node, CMP began to transition from a ‘process simplifier’ to a ‘process enabler’ step. Expanding applications of CMP have made possible the integration of FinFET, RMG (Replacement Metal Gate) and TSV (Through-Silicon-Via)[1].

In sub 1x logic fabrication, the total number of CMP steps may reach 20 or more. Use of FinFET technology in 1x and sub 1x provides much better performance at the same power budget or equal performance at a much lower power budget compared to planar mode[2]. Further, III-V compounds are expected to be integrated at 5nm technology node. III-V materials enable V_dd scaling to address power without sacrificing performance due to the very high electron injection velocity at virtual source compared to Si[3]. These III-V films will require CMP with special care due to the probability of toxic gas release (AsH₃/PH₃).

Beyond 5nm, it is widely assumed that FinFET technology will not be able to provide the small scale features and therefore, gate-all-around technology will be used. To implement gate-all-around, one potential pathway may be to use 2D TMD (2 dimensional transition metal dichalogenide) films. 2D TMD gate-all-around film allows for increasing direct S/D (source/drain) tunneling[4].

With new types of films getting integrated in smaller features, it is necessary therefore to understand the type and nature of various films being used to fabricate devices using sub 1x nm features. In this paper, various US patent applications by leading device manufacturers within the past year will be reviewed to explore the most important CMP steps needed to fabricate new devices. Further, new slurry formulation efforts to enable new CMP requirements for the sub 1x nm devices will be reviewed for the same timeline.

References:

1) Y. Moon et al, CMPUG, July 2014, San Francisco, CA.

2) C. Surisetty et al, CAMP 2013, Lake Placid, NY.

3) T.W. Kim, IEDM 2012.

4) K. Majumdar et al, EDL, 35, p.402, 2014.