Chemical Mechanical Planarization is more than ever a key technology, not only in advanced CMOS fabrication but also in emerging areas like the “Internet Of Things” (IOT). Whereas lower nm-CMOS-nodes require a perfect process control with nearly zero within-wafer-non-uniformity, “atomic layer CMP”, IOT applications introduce an almost unlimited number of new and partly contradictory process demands. “Crazy” layouts are accompanied by various substrate diameters and thicknesses. The list of materials, which need to be planarized, is almost as long as the periodic table of elements. On the other hand, the requirements on planarity and surface quality are not much less challenging than for advanced CMOS. All that comes along with a modest number of wafers. In conclusion, IOT device fabrication needs highly flexible CMP setups, which ensure a process quality and performance comparable to advanced CMOS fabrication. Actually, this is needed not only for fabrication but also for any process development and research in this field.

How to deal with this situation? State of the art CMP equipment will certainly give the desired process quality, however, it is mostly dedicated to high throughput at specific process settings. One advantage of modern equipment is that advanced membrane heads are very forgiving when it comes to wafer thickness variation.  The capability to handle substrate sizes with a reasonable conversion effort, however, is limited. Moreover, these machines are tremendously expensive in procurement and operation. Even refurbished equipment of a recent generation will only partially solve this problem.  For research facilities like Fraunhofer, and probably for some small and medium IOT device manufactures, such tools are not a viable option financially. Against this background, depreciated legacy tools become an interesting alternative. The market is filled with this type of equipment. Refurbishing companies, often specialized to these machines, are able to give them a second life. The major issue: How to achieve the necessary process performance with reasonable conversion effort? In order to achieve exactly that, the equipment needs to be upgraded with state of the art/advanced options, such as advanced membrane polish heads (carriers).

Within this paper we will present process results obtained from a remanufactured IPEC CMP tool, equipped with advanced membrane carriers. The necessary tool modification comprises a complete reconstruction of polish arm inner workings as well as new hardware and software to control the carrier, which will be briefly explained. As a result of this work, the tool is made able to work with 150 mm and 200 mm membrane carriers without tremendous conversion effort. Running the equipment in manual or semi automatic mode, as usually done in research and development environments, requires less than 15 minutes for a diameter change.  For CMP of dielectric, Figure 1 shows that the upgraded head produces not only better non-uniformity for 200mm wafers, but also opens up the process parameter window to allow for improved removal rate as well. In addition, a 100mm membrane carrier has been recently developed.  This carrier enables for the first time the advanced process capability of CMP for the 100mm non-Si wafers being used for the development of many novel devices. Figure 2 demonstrates that the non-uniformity, removal rate, and profile tunability of advanced carriers is now available for 100mm wafers.

The main objective of this paper is to work out important process characteristics, such as within wafer non-uniformity and reproducibility. To that, a series of experiments was carried out and will be explained in detail. Based on the result we will discuss opportunities and limitations of such a tool modification. Finally, we will give selected application examples.