Recently, a new type of nano-resistor device made from the high-k dielectric MOS structure was reported [1-5]. Nano-resistors are formed after a dielectric breakdown process. The nano-resistors are conductive paths that allow the current flowing from the substrate to the gate but not in the other direction [4]. In addition to light emission, it shows the antifuse- and diode-like characteristics [3,4]. For the antifuse application, it has a large current ratio of >10⁵ between the “programmed” and “unprogrammed” states [3]. Previously, it was reported that the Schottky contact was formed between the conductive path and the Si substrate after the hard dielectric breakdown [6]. In this paper, authors investigated the resistivity of the nano-resistor surrounded by the Zr-doped HfO2 (ZrHfO) high-k dielectric and its Schottky contact barrier height with Si.

The nano-resistors were formed from the dielectric breakdown of a MOS capacitor with the ZrHfO high-k film deposited on top of a p-type <100> Si (11-20 Ω∙cm) wafer. The detailed fabrication process of the 300 µm-diameter MOS capacitor and the nano-resistor formation step could be found in refs. 1-5. The sample surface was imaged with the JEOL JSM-7500F SEM after being stressed at the gate voltage (V_g) of -20 V for 20 min. The I-V curve was measured with an Agilent 4155C semiconductor parameter analyzer.

Figure 1 shows the top view of the device after being stressed at V_g = -20 V. Many tiny bumps are evenly distributed across the electrode surface. Each bump correspond to a nano-resistor of which the rough surface is formed from the high local temperature generated from the current flow [1]. The actual nano-resistor is located in the center of the bump and is much smaller than the size of the bump [5]. The total cross-sectional area ratio of bumps to the gate in the Fig. 1 structure is estimated to be approximately 0.04443.

Figure 2 shows the I-V curve of the nano-resistor device. In the large voltage range, the current increases linearly with the increase of the magnitude of V_g (|V_g|). It has a constant resistance (R_s) of 396.6 Ω. It is composed of several resistors connected in series: the bulk Si wafer, the Schottky contact between the Si and the nano-resistor, the nano-resistor, the ohmic contact between the nano-resistor and the gate, and the ITO gate electrode. The bulk Si resistance can be calculated based on ref. 7. At the large |V_g|, the Schottky contact resistance is negligibly small compared with other resistances. If the ohmic contact and gate electrode resistances are also neglected, the total resistance of the nano-resistors can be estimated. We assume that each nano-resistor has the same resistivity. Then, the resistivity of the nano-resistor is estimated to be 2673–7075 Ω∙cm, which is in the order of 10³ Ω∙cm.

At the low |V_g| range, we used the Schottky contact equation to fit the device’s I-V curve, as shown in equations 1 and 2 [7]. The voltage drop across the Schottky contact is taken as V-IR_s. Figure 3 shows that the Schottky contact equation fits well with the experimental data and the nano-resistor has a barrier height of 0.66 eV on Si.

In summary, the resistivity and barrier height of the nano-resistor can be estimated from the experimental data based on some basic assumption of the material properties.

[1] Y. Kuo et al, APL, 102, 031117 (2013).

[2] Y. Kuo, IEEE TED, 62, 3536-3540 (2015).

[3] Y. Kuo, ECST, 67, 183 (2015).

[4] Y. Kuo, ECST, 69, 23 (2015).

[5] C.-C. Lin et al, APL, 106, 121107 (2015).

[6] A. Avellán et al, IEEE EDL, 29, 366 (2008).

[7] S. M. Sze et al, Physics of Semiconductor Devices, John Wiley & Sons, New Jersey (2007).