Poly-Si Planarization by ICP Plasma Etch at FinFET Technology

Tuesday, 30 May 2017
Grand Ballroom (Hilton New Orleans Riverside)
Y. Wang (Semiconductor Manufacturing International Corporation), Q. Han (Semiconductor Manufacturing International Corp.), and H. Zhang (Semiconductor Manufacturing International Corporation)


The fin field effect transistors (FinFET) have been extensively explored for many years and recently mass production have been realized for its superior properties in solving short channel effects and size-down requirements. [1]

In FinFET technology node, the topography started to turn worse due to the introduction of the three-dimensional (3D) fin structures. The control became one of the most important issues in FEoL. In poly-gate loop, the lithography window and poly silicon etch profile will be limited by the surface topography and thus affect the device performance as well as the yield improvement. To improve the poly-silicon topography after the CMP process becomes very important.

In this paper, we report the poly-silicon planarization with the introduction of the matrix-temperature controller, named as Hydra, which is equipped in one commercial inductive coupled plasma (ICP) etch tool. The 3sigma of poly-silicon thickness within improved 80% and the uniformity is very close to current planar technology node, as shown in Figure 1. The temperature dependence is 21.7A/. The planarization results show better performance than gas cluster ion beam (GCIB) method as reported. [2]

For more common use, an advanced process control is also proposed to overcome the difference of incoming after CMP process. The CMP process always shows a major radical thickness map, which can be compensated by tuning radical etch rate map by changing process parameters. The Hydra based etch planarization technology can also be extend to other process as ILD etch back with suitable etch process. This technology will be very power in the future 3D transistors for planarization.

This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type). The authors would like to thank Mr. Kui Wang, Mr. Jiangang Liu, and Dr. Yushan Chi from Lam research for the support of constructive discussion.


[1] C. Auth et al., “A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” in VLSI Symp. Tech. Dig., pp. 131–132, 2012,

[2] T. Kagalwala et al., “Integrated metrology's role in Gas Cluster Ion Beam etch”, 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), pp. 72-77, 2015