Frequency and Area Dependence of High-K/Ge Mos Capacitors

Wednesday, 31 May 2017: 16:00
Churchill B2 (Hilton New Orleans Riverside)
I. Mitevski, Y. Ding, and D. Misra (New Jersey Institute of Technology)
AbstractGe substrate devices in Complementary Metal Oxide Semiconductors (CMOS) technology have been extensively studied due to its high electron and hole mobility [1]. However, most of the Ge devices have some limitation as making a high-quality Ge/High-k gate stack is rather difficult compared to Si/High-k system. The purpose of this work is to further study the capacitance measurements of a MOS capacitor at different frequencies for square devices with different side lengths (10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 100 μm). The series resistance corrected capacitance (Cc) for accumulation region increases on a faster pace when a lower frequency (1KHz) is used than at a higher frequency (1MHz) (Figure 1(a)) as a function of side length, a. Accumulation capacitance has a strong dependence on frequency in metal oxide semiconductor devices. Our devices follow the same trend as previous studies have reported [2]. On the other hand, our study shows substantial decrease of Cc per unit area in Ge/High-K in comparison to High-K/Si devices (Figure 1(b)). This decrease is attributed to the large non-uniform interface defect density [3], high leakage current [3] associated with Ge stacks and fringing field effect [4]. Capacitance at accumulation condition depends on interface capacitance (Cit) which changes with defects density. Defect density increases proportionally with area and High-K/Ge devices, being leakier, experience a higher decrease of Cc per unit area than High-K/Si devices. The impact of fringing field capacitance (CL) on parallel plate capacitance (CP) decreases when device area is increased (Figure 1(c)) and this contributes to further decrease in total capacitance Cc per unit area. This work explains the frequency dispersion of high-k MOS capacitance in accumulation region and the unit capacitance decrease when Ge substrate is used. The study also models the fringing field capacitance [5] and its effect on MOS devices.

Figure 1 (a) Corrected capacitance (Cc) measured at -1.5 V (accumulation) at 1 MHz and 1 KHz shows frequency dependence; (b) Unit Capacitance is plotted against area for Ge substrate and Si substrate sample for measurements at frequency of 1MHz. Cs is substrate capacitance and Cox is oxide capacitance; (c) CL/CP as a function of area. CL and CP are calculated as per Yuan & Trick’s model [5].

[1] D. Kuzum, A. J. Pethe, T. K., K. C. S, IEEE T. Electron. Dev., vol. 56, p. 648, 2009.

[2] P. R. Lee, J. R. Ruzyllo, Electrochemical Society, vol. 9, p.353-362, 2007.

[3] Y. M. Ding, D. Misra, J. Vac. Sci. Technol. B, vol. 34, p. 021203 2016.

[4] S. Maurya, B. R. Singh, Solid States Physics, AIP Conf. Proc. 1512, 742-743, 2013.

[5] E. Barke, IEEE Transactions on Computer Aided Design, vol. 7, No. 2, 1988.