High-k/Metal Gate System 
In accordance with the requirement of CMOS scaling, replacement of thermally grown SiO2 gate dielectric with other dielectric materials with higher dielectric constant (k) has become imperative to reduce the equivalent oxide thickness (EOT) to achieve higher drivability of FET. Key factors on Hf-based high-k/metal gate (HK/MG) CMOS technology based on conventional gate first process for low operational power application are overviewed. Work-function (WF) tuning derived from ionic property of high-k material, process cost, EOT scaling with low gate leakage current are issues to be overcome. Among them, the key issue is how to control the atomic distribution in the Hf-based HK/MG system, which is absolutely requisite for WF tuning and EOT scaling.
Interpretation of effective work-function (WF): For conventional gate first process, due to the interfacial reaction, the Fermi level is pinned and the WF increases with decreasing the EOT. In addition to this, due to the fixed charge in the high-k dielectric, the WF is also modulated, hence the effective WF (eWF) changes. The effect of the fixed charge is rather complicated due to an oxygen vacancy behavior in HK. Consequently, the eWF results in the “roll-off” behavior caused by the (+) charge induced by the oxygen vacancy. When the oxygen increases, i.e., (-) charge increases in the HK, the obtained WF tends to roll-up. In contrast, it tends to roll-off for more (+) charge induced by oxygen vacancy, Vo2+in the HK.
Formation process of Hf-based high-k (HK): Generally, HK is deposited by metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD), however, HK dielectric formation by oxidizing a preliminarily sputtered metallic-Hf is reasonable approach for fabricating the HK gate stack in a very pure form with less water content across the wafer. And in a very important thing, by controlling the oxidation time, this process can provide precise thickness control of the interfacial layer (IL) including “zero IL” with excellent uniformity.
Magnetic Tunneling Junction
A magnetic tunnel junction (MTJ) for spin-transfer-torque (STT) switching is a promising building block of non-volatile working memory embedded in very large scale integrated circuits (VLSIs) because of its potential to reduce a power consumption by replacing the conventional volatile cache memories. Among many materials, a CoFeB/MgO/CoFeB stack structure has attracted much attention as a candidate of MTJ embedded in VLSIs because of its high tunnel magnetoresistance (TMR) ratio caused by a perpendicular magnetic easy axis. And what is better, this MTJ has a potential for high integration into VLSIs down to a junction size of 1X nm regime. To improve the MTJ performance, crystal structure of the CoFeB/MgO interface is a crucial issue as well as B behavior during the process treatment.
Redox reaction: As an example of the interfacial reaction, a redox reaction was observed at the surface of Ta/CoFeB/MgO/CoFeB MTJ stack after annealing up to 400℃ for 1 h in vacuum, by angle-resolved X-ray photoelectron spectroscopy (XPS). For 1nm-thick tantalum capping layer of the as-deposited stack sample, both the tantalum layer and the surface of the CoFeB layer underneath the tantalum layer were naturally oxidized. By comparison of the Co 2p and Fe 2p spectra with respect to as-deposited and annealed samples, reduction of the naturally oxidized cobalt and iron atoms was found to occur at the surface of the CoFeB layer. This reduction reaction was more significant at higher annealing temperature. Oxidized cobalt and iron were found to be reduced by boron atoms that diffused toward the surface of the top CoFeB layer. By means of naturally oxidized surface of the CoFeB layer formed on SiO2, the redox reaction behavior after annealing was confirmed by angle-resolved XPS analysis. This redox reaction is thermodynamically reasonable according to the Ellingham diagram.
(This work is supported by Industrial Affiliation on the STT-MRAM program in CIES Consortium and ACCEL project under JST.)
 M. Niwa (2013), Chapter 4, High Permittivity Gate Dielectric Materials, Edited by S. Karr, Springer Series in Advanced Microelectronics 43, pp. 191-234.
 S. Sato et al., Appl. Phys. Lett. 196, 142407 (2015).