In CMOS manufacturing industry, device threshold voltage (V_t) stability is a pre-requisite for volume manufacturing. Device architectural elements, process parameters and room temperature aging (Q-time) are the main source of V_t instability. In FinFET technology with metal/high-K gate, device V_t is controlled through effective work function engineering by optimal metal layer thickness as well as controlled Aluminum (Al) doping/diffusion within the gate stack [1-4]. The device V_tcan also be influenced by its architectural elements and process parameters [5] which should be well controlled during the volume manufacturing. However, room-temperature Q-time effects at several stages of the manufacturing process are practically unavoidable.

This work demonstrates post n-work function (WF) deposition Q-time impact on device V_t instability. Longer Q-time induced V_t shifts that are independent of gate length and number of fins, as seen in Figure 1. The root cause investigations were performed using device characterization followed by elemental analysis of the gate stack (Figure 2). It was found that, the content of oxygen (O₂) and Al in the gate stack is well correlated to post n-WF deposition Q-time. The device V_t instability can be explained by oxygen incorporation due to n-WF layer oxidation during the Q-time post n-WF deposition and the corresponding reduction of Al diffusion into the high-K capping layer [2, 6]. In this work, n-WF layer thickness/composition was optimized to enable immunity to a larger Q-time limit for volume manufacturing, as demonstrated in Figure 3 from n-WF layer recipe group A to group C. The reliability impact of the gate stack was also assessed. Device benefits such as T_inv scaling and thereby I_on-I_offperformance improvement was also demonstrated without compromising the reliability.

Reference

[1] L.P.B. Lima et al, J. Appl. Phys., 115, 074504, 2014

[2] A. Veloso et al, Jpn. J. Appl. Phys.52. 04CA02, 2013

[3] L. Kornblum et al, Appl. Phys. Lett., 100, 062907, 2012

[4] C.L. Hinkle et al, Appl. Phys. Lett.,96, 103502, 2010

[5] M. Togo et al, VLSI tech. Symp. Dig.pp. 140-141, 2014

[6] A. Veloso et al, VLSI Tech. Symp. Dig. pp. 34-35, 2011.