(Invited) Probing the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations

Wednesday, 4 October 2017: 15:10
Chesapeake D (Gaylord National Resort and Convention Center)
G. Pourtois (University of Antwerp, Belgium, imec, Belgium), A. Dabral (imec, Belgium, KULeuven, Belgium), K. Sankaran (imec, Belgium), W. Magnus (imec, Belgium, University of Antwerp, Belgium), H. Yu, A. de Jamblinne de Meux (imec, Belgium, KULeuven, Belgium), A. K. A. Lu (MathAM-OIL, Japan), S. Clima (imec, Belgium), K. Stokbro (Quantumwise, Denmark), M. Schaekers (imec, Belgium), M. Houssa (KULeuven, Belgium), N. Collaert, and N. Horiguchi (imec, Belgium)
Over the last technology nodes, the continuous reduction of the CMOS dimensions has been pushing the physical limits of the transistor into numerous ends. Consequently, a straightforward linear scaling of device dimensions does not apply anymore to all the aspects of the CMOS transistor. For instance, the aggressive scaling of the transistor gate pitch requires that both the gate length and the S/D contact dimensions are reduced in size; constraining the gate, the sidewall spacers and the S/D contacts to compete continuously for space. On the other hand, the transistor gate length has also to follow a different scaling law and is kept as large as possible to ensure a proper electrostatic control. A direct consequence of this approach is the need to keep on decreasing the S/D contact resistance, which currently constitutes a new bottleneck in the scaling of modern CMOS. Aside from being able to reduce the physical dimensions of the contact, it is paramount to minimize the metal/semiconductor intrinsic resistivity which has now become a major roadblock to be conquered. Recently, the cumulated efforts of the scientific and engineering communities have substantially extended the physical limits of the S/D contact resistance thanks to the increase in the concentration of activated dopants in the semiconductors and to the engineering of their Schottky barrier. The latter is achieved by integrating metals with a weak Fermi level pinning at the interface with the semiconductor. As a result, contact resistivities as low as 2x10-9 Ω.cm2 [1] and 8.4x10-10 Ω.cm2 [2] have been reported for n-Si-TiSi(amorphous) and p-Si30Ge70-TiSi(amorphous) with dopant concentrations as high as 6x1020cm-3 and 1x1021cm-3[1,2]. Although these accomplishments are very impressive, little is known on the intrinsic limits that will ultimately determine the contact resistivity and it remains unclear whether even higher doping concentrations would be desirable or not.

In this contribution, we will report a fundamental study of the factors that set the contact resistivity between metals and highly doped semiconductors. We will investigate the case of n-type doped Si contacted with amorphous TiSi combining first-principles calculations with Non-Equilibrium Green functions transport simulations [4][5]. We will show that, whereas the metal/semiconductor intrinsic contact resistivity initially scales with the doping concentration, it is found to saturate at ~2x10-10 Wcm2, as of a doping concentration of ~5x1021 cm-3. From this concentration on, electron injection is governed by Ohm’s law. It turns out that, in such high doping regimes, the electron injection does no longer depend on the barrier height set by the interface potential to be crossed. In turn, it becomes less sensitive to the chemical composition of the interface/degree of disorder and is limited by the intrinsic transmission probability of electrons being injected from the metal into the semiconductor. The latter depends on both the effective masses of the metal and of the semiconductor [3] and imposes an intrinsic physical limit to the contact resistance. We will show that, in this regime, contacting metals with a heavy electron effective mass are favorable to increase the transmission probability and, hence, to reduce of the semiconductor-metal intrinsic contact resistivity.


The authors thank the imec industrial affiliation core CMOS program and quantumwise for financial and technical supports, respectively.


  1. Hao Yu, Marc Schaekers, Jian Zhang, Lin-Lin Wang, Jean-Luc Everaert, Naoto Horiguchi, Yu-Long Jiang, Dan Mocuta, Nadine Collaert and Kristin De Meyer, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 64, no. 2, pp.500 (2017).
  2. Hiroaki Niimi, Zuoguang Liu, Oleg Gluschenkov, Shogo Mochizuki, Jody Fronheiser, Juntao Li, James Demarest, Chen Zhang, Bei Liu, Jie Yang, Mark Raymond, Bala Haran, Huiming Bu, and Tenko Yamashita, IEEE ELECTRON DEVICE LETTERS, vol. 37, no. 11, pp. 1371 (2016).
  3. Ashish Baraskar, A. C. Gossard, and Mark J. W. Rodwell, Journal of Applied Physics, Vol. 114, pp. 154516 (2013).
  4. Atomistix ToolKit version 2016.1, QuantumWise A/S (www.quantumwise.com).
  5. M. Brandbyge, J.-L. Mozos, P. Ordejón, J. Taylor, and K. Stokbro, Phys. Rev. B 65, pp. 165401 (2002).