From previous studies on MIS tunneling diode (MIS TD) with surrounding MOS capacitor devices, I-V characteristics of MIS TD changed when various gate voltages of surrounding device were applied. [1] [2] However, the C-V behavior hadn’t been discussed before. In this work, in order to understand the mechanism of carrier transportation, C-V measurement on MIS TD under low to high frequencies was practiced in the meantime of I-V measurement. From the different response of inversion charge to gate voltages and to frequencies, a new vision of minority carrier modulation by surrounding device is proposed in this letter.

The device set under study is shown in Fig. 1, composed of an inner round-shaped MIS TD, and an outer circle of MOS capacitor device which fully surrounds the inner MIS TD; in addition to substrate, there were three terminals for each device set. The inner MIS TD was designed with a gate area of ~2.2x10⁴ μm² (radius 83.6 μm), and the spacing to the outer gate is 12.6 μm, which is defined by lithography and wet etch. With an equivalent oxide thicknesses (EOT) of 32A, the gate dielectric of inner and outer devices was both made of SiO₂grown by anodized oxidation process at the same time on a P-type substrate. [3]

In Fig. 2a and 2b show the I-V and C-V (at AC 1 kHz) characteristics of the inner MIS TD respectively (I_TD-V_TD and C_TD-V_TD), under various outer gate bias (Vg). Firstly, when Vg was biased at flat-band voltage of the outer device (black lines, Vg=V_FB= -0.9V), the I_TD saturated at ~5pA at positive V_TD, because the substrate depleted and the minority carriers were limited due to absence of supply of electrons, also reflected in the low C_TD at inversion side. As Vg changing to >V_FB (-0.3V~+1V), the I_TD at positive V_TD increased significantly (~1000X of Vg= -0.9V at V_TD 1.5V), and unlike the saturation behavior when Vg= -0.9V, I_TD exponentially increased with greater V_TD. Meanwhile, C_TD-V_TD of Fig. 2b showed more capacitance response at inversion side (blue line). These changes in I-V and C-V characteristics were explained by the appearance of excess minority carriers, which are believed to be supplied from the inversion layer under the outer gate (Vg > V_FB). From multiple-frequency C_TD-V_TD in Fig. 2c, it was learned that enough time is still required for the minority carriers to response to V_TD.

Another device set with a thinner EOT of 22A was studied through similar I-V and C-V analyses. As Fig. 3b shows, unlike the device set with EOT 32A, the C_TD-V_TD response at inversion side for Vg>V_FB disappeared. After checking the current flows among inner gate, outer gate and substrate, much greater gate leakage at outer device was found. The model proposed was that most of the electrons preferred directly tunneling through outer gate instead of diffusing to neighboring inner gate. As a result, a much less I_TD change (~7X) as Vg switched from -0.9V to 0V than the device set with an EOT of 32A (~1000X), as shown in Fig. 3a. Moreover, even lower I_TDat greater Vg= 1V also indicated that more serious direct tunneling at outer gate was taking away the supply of minority for inner MIS TD.

In this work, the mechanism of Vg influence on I_TD-V_TD was modeled by the modulation of minority carriers through C-V and I-V analyses. To achieve higher I_TDOn/Off ratio, besides the supply of minority carriers, the prevention of minority carriers leaking through the outer gate is essential as well.

This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 105-2221-E-002-180-MY3.

References:

[1] C. S. Liao and J. G. Hwu, IEEE Trans. Electron Devices, vol. 62, no. 6, (2015)

[2] C. S. Liao and J. G. Hwu, IEEE Trans. Electron Devices, vol. 63, no. 7, (2016)

[3] C. C. Ting, Y. H. Shih, and J. G. Hwu, IEEE Trans. Electron Devices, vol. 49, no. 1, (2002)