The device set under study is shown in Fig. 1, composed of an inner round-shaped MIS TD, and an outer circle of MOS capacitor device which fully surrounds the inner MIS TD; in addition to substrate, there were three terminals for each device set. The inner MIS TD was designed with a gate area of ~2.2x104 μm2 (radius 83.6 μm), and the spacing to the outer gate is 12.6 μm, which is defined by lithography and wet etch. With an equivalent oxide thicknesses (EOT) of 32A, the gate dielectric of inner and outer devices was both made of SiO2grown by anodized oxidation process at the same time on a P-type substrate. 
In Fig. 2a and 2b show the I-V and C-V (at AC 1 kHz) characteristics of the inner MIS TD respectively (ITD-VTD and CTD-VTD), under various outer gate bias (Vg). Firstly, when Vg was biased at flat-band voltage of the outer device (black lines, Vg=VFB= -0.9V), the ITD saturated at ~5pA at positive VTD, because the substrate depleted and the minority carriers were limited due to absence of supply of electrons, also reflected in the low CTD at inversion side. As Vg changing to >VFB (-0.3V~+1V), the ITD at positive VTD increased significantly (~1000X of Vg= -0.9V at VTD 1.5V), and unlike the saturation behavior when Vg= -0.9V, ITD exponentially increased with greater VTD. Meanwhile, CTD-VTD of Fig. 2b showed more capacitance response at inversion side (blue line). These changes in I-V and C-V characteristics were explained by the appearance of excess minority carriers, which are believed to be supplied from the inversion layer under the outer gate (Vg > VFB). From multiple-frequency CTD-VTD in Fig. 2c, it was learned that enough time is still required for the minority carriers to response to VTD.
Another device set with a thinner EOT of 22A was studied through similar I-V and C-V analyses. As Fig. 3b shows, unlike the device set with EOT 32A, the CTD-VTD response at inversion side for Vg>VFB disappeared. After checking the current flows among inner gate, outer gate and substrate, much greater gate leakage at outer device was found. The model proposed was that most of the electrons preferred directly tunneling through outer gate instead of diffusing to neighboring inner gate. As a result, a much less ITD change (~7X) as Vg switched from -0.9V to 0V than the device set with an EOT of 32A (~1000X), as shown in Fig. 3a. Moreover, even lower ITDat greater Vg= 1V also indicated that more serious direct tunneling at outer gate was taking away the supply of minority for inner MIS TD.
In this work, the mechanism of Vg influence on ITD-VTD was modeled by the modulation of minority carriers through C-V and I-V analyses. To achieve higher ITDOn/Off ratio, besides the supply of minority carriers, the prevention of minority carriers leaking through the outer gate is essential as well.
This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 105-2221-E-002-180-MY3.
 C. S. Liao and J. G. Hwu, IEEE Trans. Electron Devices, vol. 62, no. 6, (2015)
 C. S. Liao and J. G. Hwu, IEEE Trans. Electron Devices, vol. 63, no. 7, (2016)