Impact of Alkaline Solutions on Via Resistance Reduction and Critical Dimension (CD) Control for Sub-10 Nm Technology Nodes

Thursday, 5 October 2017: 11:20
Chesapeake D (Gaylord National Resort and Convention Center)
K. Ryan (GLOBALFOUNDRIES), B. Peethala (IBM Research), H. You (GLOBALFOUNDRIES), R. Knarr (Lam Research Corporation), F. Mont (GLOBALFOUNDRIES), D. Canaperi (IBM Research), W. Kleemeier, P. Mennell, R. Quon, and S. Siddiqui (GLOBALFOUNDRIES)
The continued scaling for back-end-of-line (BEOL) for the sub-10 nm node poses significant challenges due to the shrinkage in dimensions and reduced Cu volume. Specifically for via, a clean interface between the underlying metal (Cu, Co) and Ta/TaN liner is required to reduce additional resistance-capacitance (RC) delays. Traditionally, fluoride based wet chemical systems are used to remove CuOx and post etch residues from the ultra-low k (ULK) dielectric sidewalls [1]. However, as the critical dimensions (CD) of BEOL integrated structures continue to shrink, the loss of RIE damaged low k dielectric material due to dilute HF (dHF) processing becomes a major concern. Furthermore, as Co metallization processes are being explored in interconnect structures, this necessitates an alternative to fluoride based solutions due to their incompatibility [2].

In this work, we are investigating an alternative alkaline based solutions with the addition of surfactants to prevent Cu/Co corrosion while effectively cleaning post etch residues with minimal CD loss. Some of the key parameters studied include solution concentration, oxygen levels, temperature and pH. Careful consideration was taken to adjust the solution pH by controlling the inhibitor concentration to enable Cu surface passivation while still effectively removing post etch residue (PER). As a first step, the Cu etch rates at a fixed alkaline solution concentration were measured using X-ray fluorescence (XRF) technique. Without corrosion inhibitor, Cu etch rates of 5 Å/min and 10 Å/min, respectively were measured at room temperature (RT) and 60 °C solution temperature. A significant reduction in etch rates of less than 2 Å/min was measured with the optimized inhibitor concentration in the alkaline solutions. There was no measurable change in ULK thickness for the pristine and damaged ULK films at RT, while approximately 5 Å loss at 60 °C was measured for the pristine film. Based on these results, optimized solution parameters such as concentrations, temperature, pH and process time, were developed.

A transmission electron microscope (TEM) image of the metallized via structure is presented in Figure 1. It demonstrates that via structures remain intact with a continuous metal fill and no significant removal of the exposed underlying metal layer from the alkaline based cleans process. Additionally, the impact of cleaning was electrically evaluated by measuring resistance and yield using a metal-hardmask-trench-first-via-last (MHTFVL) scheme. Results indicate equivalence in comb-serpentine and via chain yields for the optimized alkaline solution compared to the dHF process. The electrical results for the normalized isolated via chain resistance values were within ~5% of the dHF baseline as shown in Figure 2. This demonstrates the ability of the alkaline based cleaning process to remove CuOx from the bottom of the via to achieve necessary inter-level resistance targets. In conclusion, alkaline based chemistries with the addition of surfactants are a suitable alternative to dHF based cleaning methods to remove RIE based polymer residues from high aspect ratio trench and via structures while maintaining stringent CD targets for sub-10 nm technology nodes.


This work was performed by the Alliance Teams at various IBM and GLOBALFOUNDRIES Research and Development Facilities


[1] B. Peethala, F.W. Mont, S. Mollis, R. Knarr, B. L’lherron, C. Labelle, D. Canaperi, S. Siddiqui, Microelectronic Eng., 161, 98-103 (2016).

[2] V. Kamineni et al., “Tungsten and Cobalt Metallization: A Material Study for MOL Local Interconnects”, International Interconnect Technology Conference (IITC), May 23 - 26 '2016, San Jose, California, USA.