*Their high resistance states are insulating, and their low resistance states are metallic, having opposite signs of temperature sensitivity of resistance, as evidenced by resistivity data down to 18 mK.
*Their high resistance states are unstable under a mechanical pressure, which triggers them to switch to the low resistance states in less than a picosecond without any voltage assistance.
*Their low resistance states are stable under a mechanical pressure.
*Their on/off switching is triggered when their switching elements experience a critical voltage, which because of load sharing can be substantially less than the device voltage.
Since as-fabricated nanometallic memory is already in the low resistance state, it is also stable under a mechanical pressure. However, a virgin, highly resistive filamentary memory can be alternatively “formed” to the low resistance state by a pressure alone, without going through dielectric breakdown. This, along with pressure-triggered switching from the high resistance state to the low resistance state, provides unequivocal evidence that forming and switching can proceed without any ion migration, even in a filamentary memory.
In addition to the above, voltage-controlled switching is difficult to rationalize by the existing switching models for filamentary memory. These models all invoke a critical amount of electric current and joule heating to break and reconnect filaments, which are not likely to be voltage-controlled processes.
Lastly, filamentary memory has been used to emulate synapses. But all synaptic ion channels (Na or Ca) are voltage-gated. Therefore, the finding that both nanometallic and filamentary memories are voltage-controlled is fundamentally relevant to using memristors for neuromorphic computing.