(Invited) Resonant Interlayer Tunneling in 2D Van Der Waals-Materials-Based Channel-Dielectric-Channel Systems and Possible Device and Circuit Applications

Tuesday, 3 October 2017: 16:10
Chesapeake D (Gaylord National Resort and Convention Center)
L. F. Register II, G. W. Burg, C. M. Corbet, B. Fallahazad, S. Kang, K. Kim, S. Larentis, K. Lee, O. Mohammed, X. Mou, H. C. P. Movva, N. Prasad, D. Reddy, A. Valsaraj, X. Wu (The University of Texas at Austin), S. K. Banerjee (University of Texas, Austin), E. Tutuc (The University of Texas at Austin), N. Sharma, Q. Wang, M. Kim, A. Marshall (The University of Texas at Dallas), J. Xue (Shanghai Technical University), T. Taniguchi, K. Watanabe (National Institute of Materials Science), and L. Colombo (Texas Instruments Incorporated)
As the limits of CMOS performance are approached, industry, government and academia alike search for so-called beyond “CMOS devices” to replace CMOS either globally or, more likely initially, for specific applications. This discussion focuses on our ongoing efforts to develop and apply one such device concept, resonant interlayer tunnel field effect transistor (ITFETs), addressing essential physics, device design and fabrication, and circuit applications. As considered here, resonant ITFETs employ stacks of two-dimensional van der Waals materials to form both parallel conduction channels and intervening dielectric tunnel barriers. Due to the requirement for surface-parallel crystal momentum conservation between the layers, resonant tunneling between such two dimensional layers is not nominally subject to thermal smearing of the resonance over a few kBT as in more conventional resonant tunneling systems. Thus, such interlayer resonant tunneling potentially could be used for low voltage room temperature applications, with nano-scale devices operating at a tenth of a volt or less in principle. In addition, this layered 2D geometry readily lends itself to electrostatic gating of the interlayer tunneling, from above and even below. The concept of such interlayer resonant tunneling has been around for years. However, the use of 2D van der Waals materials such as monolayer or Bernal-stacked bilayer graphene as channel materials, hexagonal boron-nitride (hBN) as dielectrics, and/or various transition metal dichalcogenides such as MoS2 or ReS2 as channel or dielectric materials, in various combinations also lends itself to atomically precise control of layer thicknesses and interfaces, avoiding, e.g., inhomogeneous resonance broadening. However, there are many challenges to achieving such resonant ITFETs and using them in circuit applications. For example, rotational alignment between layers is essential to interface-parallel crystal-momentum conserving resonant tunneling for van der Waals channel materials with peripheral band edge energy valleys, which is the norm. At least in experimental device fabricated via layer exfoliation, crystallographic alignment between the channel layers had been challenging to achieve. However, among the authors, we recently achieved a breakthrough in this respect allowing very precise control over rotational alignment. Alternatively, the use of the direct gap channel material such as ReS2 should substantially remove this concern with respect to resonant broadening. However, we also demonstrate using density functional theory that rotational misalignment of the tunnel dielectric with the channel material can greatly reduce the overall amplitude of the interlayer tunneling current by, specifically, reducing the coupling across the channel-to-dielectric interfaces (vs. by band structure misalignment) even with rotational alignment between the channel layers. Toward eventual nanoscale devices, we show that Heisenberg position-momentum uncertainty translated to energy uncertainty via the carrier group velocity, dE/d(ħk), will lead to resonance broadening, and the more so for fast carrier. Another concern is intrinsic spectral broadening of the crystal momentum states by scattering. Nevertheless, if fabrication issues could be overcome, we show that low-voltage operation of nanoscale devices should be possible. However, the negative differential resistance (NDR)-current-voltage (I-V) characteristics of these devices make use in conventional circuits challenging. The use of clocked power supplies allows basic logic gates such as inverters, buffers, and NAND and NOR gates to be created. It also results in each gate effectively being a latch, but also effectively having an activity factor of unity for each clock cycle, which requires new approaches to higher level circuit design. We show that for certain applications such as ultra-deep pipelining and ultra-compact circuits, and perhaps non-conventional computing schemes, resonant ITFET circuits could provide advantages over CMOS. (This work is supported by the Nanoelectronics Research Initiative (NRI) through the Southwest Academy of Nanotechnology (SWAN)).