In this work, a novel Si-based test chip was utilized to perform in-plane ZT measurements of PbTe/PbSe superlattice films. Figure 1 (a) shows the pre-fabricated circuit on the chip for measuring simultaneously the Seebeck coefficient, electrical conductivity, and thermal conductivity . The thermoelectric film was deposited in the red square area by using a shadow mask. All the parameters were measured in the temperature range of 120 K to 450 K with a 1 T magnet field. In our work, PbTe and PbSe thin films and superlattice layers were synthesized by Atomic Layer Deposition (ALD) technology directly on the pre-structured Si chip. Figure 1 (b) shows an SEM micrograph of the 30 nm thick PbSe film grown on the chip. The PbTe/PbSe superlattice was then deposited on the PbSe buffer layer using ALD by alternatively depositing PbTe and PbSe layers. A thin Al2O3protection and diffusion barrier layer was applied to avoid oxidation and degradation of PbTe/PbSe films. The period of superlattice structure was varied from 2 nm to 10 nm to observe optimized period for achieving highest ZT value.
. Linseis, V., Völklein, F., Reith, H., Woias, P., & Nielsch, K. Platform for in-plane ZT measurement and Hall coefficient determination of thin films in a temperature range from 120 K up to 450 K. Journal of Materials Research, 31(20), 3196-3204, (2016).