In-Plane ZT Measurements of PbTe/PbSe Superlattice Layers Deposited by Atomic Layer Deposition

Wednesday, 4 October 2017
Prince George's Exhibit Hall D/E (Gaylord National Resort and Convention Center)
X. Chen (Applied Research Center), V. Linseis (Linseis Messgeräte GmbH), P. Lin (Applied Research Center), K. Zhang (Old Dominion University), H. Baumgart (Old Dominion University, ECE Department), and H. Reith (Leibniz-Institute for Solid State and Materials Research)
The conversion efficiency of the thermoelectric (TE) device is determined by the dimensionless figure of merit ZT, which is expressed as ZT = S2σT/κ, where S is the Seebeck coefficient, σ is the electrical conductivity, κ is the thermal conductivity, and T is the absolute temperature. The key strategy to enhance ZT involves the reduction in thermal conductivity k of TE materials. This led to the synthesis of low-dimensional structured materials such as 2-D superlattice structure, 1-D nanowire, and 0-D quantum dots. The phonon transport was suppressed if the dimension of the film approaching the mean free path of the phonons, resulting in a reduction in thermal conductivity and consequently improves ZT. The direction of the measurement, either in-plane or vertical to the surface, plays an important role in determining TE properties of the anisotropic samples, such as superlattices and quantum well structures. It is essential to measure all the parameters in the same direction and simultaneously to obtain accurate ZT value.

In this work, a novel Si-based test chip was utilized to perform in-plane ZT measurements of PbTe/PbSe superlattice films. Figure 1 (a) shows the pre-fabricated circuit on the chip for measuring simultaneously the Seebeck coefficient, electrical conductivity, and thermal conductivity [1]. The thermoelectric film was deposited in the red square area by using a shadow mask. All the parameters were measured in the temperature range of 120 K to 450 K with a 1 T magnet field. In our work, PbTe and PbSe thin films and superlattice layers were synthesized by Atomic Layer Deposition (ALD) technology directly on the pre-structured Si chip. Figure 1 (b) shows an SEM micrograph of the 30 nm thick PbSe film grown on the chip. The PbTe/PbSe superlattice was then deposited on the PbSe buffer layer using ALD by alternatively depositing PbTe and PbSe layers. A thin Al2O3protection and diffusion barrier layer was applied to avoid oxidation and degradation of PbTe/PbSe films. The period of superlattice structure was varied from 2 nm to 10 nm to observe optimized period for achieving highest ZT value.


[1]. Linseis, V., Völklein, F., Reith, H., Woias, P., & Nielsch, K. Platform for in-plane ZT measurement and Hall coefficient determination of thin films in a temperature range from 120 K up to 450 K. Journal of Materials Research, 31(20), 3196-3204, (2016).