As the number of stacked layers of the 3D NAND structure increases, the memory density of 3D NAND flash memory device increases [1]. In the fabrication of 3D NAND device, it is essential to selectively etch Si₃N₄ by an etchant flowing along a narrow slit followed by metal deposition. However, as the number of Si₃N₄/SiO₂ multi-stack increases, selective etching of Si₃N₄ becomes difficult. In order to increase the Si₃N₄-to-SiO₂ etch selectivity, SiO₂ etching inhibitor should be added to H₃PO₄. Unfortunately, most of SiO₂ etching inhibitors added to H₃PO₄ generate oxide regrowth around SiO₂ layer on the Si₃N₄/SiO₂ multi-stack structure. In this study, the mechanism of oxide regrowth occurred on the 3D NAND structure was investigated.

Patterned Si₃N₄/SiO₂ multi-stack structures were prepared. Etching experiments were performed using coupon wafers in 85% H₃PO₄ or etching inhibitor-added H₃PO₄ at 160 °C. The Si₃N₄ and SiO₂ etching rates and Si₃N₄-to-SiO₂ etch selectivity were measured using spectroscopic ellipsometry and oxide regrowth on the Si₃N₄/SiO₂ multi-stack structure was analyzed using FE-SEM and HR-TEM.

When the Si₃N₄/SiO₂ multi-stack structure was etched in the SiO₂ etching inhibitor-added H₃PO₄, oxide regrowth was observed on the SiO₂ layered trenches on the Si₃N₄/SiO₂ multi-stack structure, as shown in Fig. 1. The oxide regrowth occurred intensively at the corner of SiO₂ layered trench and oxide regrowth occurred heavily at the bottom of Si₃N₄/SiO₂ multi-stack structure as compared to the top. The overall amount of oxide regrowth on the SiO₂ layered trench increased as the concentration of SiO₂ etching inhibitor added to H₃PO₄ increased. In addition, it is shown that generation rate of etching product is an important factor to occur oxide regrowth. Based on the results, it is suggested that etching inhibitor addition and high generation rate of etching product and mass transfer limitation are responsible for the oxide regrowth. Through their optimization, selective Si₃N₄ etching on the Si₃N₄/SiO₂ multi-stack structure without oxide thinning and regrowth could be obtained, as shown in Fig. 2.

References

[1] S. Aritome, NAND flash memory technologies, p. 273, John Wiley & Sons, Hoboken, NJ (2015).

[2] J. Jang, et al, in Symp. VLSI Tech. Dig., 192 (2009).