As semiconductor device scaling marching toward sub-5 nm logic, 128+ layers 3D NAND, and advanced 1x nm DRAM technology nodes, wafer surface cleaning and residue removal in nanoscale, high aspect ratio structures become increasingly critical. Dry clean technologies are developed as alternatives for traditional wet clean applications with significant advantages in process extendibility and environmental friendliness. Furthermore, in comparison with gas only processes, radicals are considered as attractive precursors for dry clean applications due to their high reactivity en route to a high cleaning efficiency.

In this work we report a novel inductively coupled remote plasma source design for radical based dry clean applications. The inductively couple plasma (ICP) source yields a high gas dissociation efficiency and a high radical density. Plasma potential and electron temperature are minimized with a unique grounded Faraday shield design and can be further suppressed with a pulsed plasma operation. Ions and electrons generated in the plasma are effectively filtered by charge separation grids, thus only leaving high flux radicals to impinge onto the wafer surface.

Different radical chemistries are developed for selective removal of different dielectric, metal, and semiconductor materials, specifically for efficient cleaning inside nanoscale and high aspect ratio structures in advanced semiconductor devices. Here we report the following applications tailored toward 3D NAND manufacturing.

Pre-epitaxial deposition clean in high-aspect-ratio channel holes: The requirements are to remove SiO_x-like residues and damaged silicon layer at the bottom of high-aspect-ratio channel holes without damage to the exposed SiO₂/SiN stacks. The aspect ratio of channel holes can exceed 50:1. A multi-step process is developed based on remote plasma chemistries containing hydrogen and fluorine radicals, in conjunction of a RF bias on wafer surface to improve directionality. SiO_x-like residues of various thickness are initially completely removed at the bottom of high-aspect ratio structures. With a customized radical chemistry and a unique anisotropic process, there is no sidewall SiN/SiO₂ damage and a minimal CD change. Followed by a selective removal of damaged silicon layer and surface contamination from prior etch process, a pristine and coherent surface can be prepared for the subsequent epitaxial deposition.

Contact hole clean: The main objective is to remove amorphous silicon or silicon oxide interface layer at bottom of high aspect ratio contact hole structures in order to minimize metal contact resistance. The aspect ratio of contact hole structures can exceed 50:1 in advanced 3D NAND devices. Device process flow requires a high selectivity towards tungsten. A fluorine-containing remote plasma process was developed to effectively remove oxidized Si residues, create enough gouging depth, and maintain contact hole structure integrity at the same time. Contact resistance is significantly reduced with the radical based dry clean process.