Computational Modeling of Copper Deposition in through Silicon Via Structures

Wednesday, 16 October 2019: 09:00
Room 210 (The Hilton Atlanta)
T. M. Braun, D. Josell, and T. P. Moffat (NIST)
Copper electrodeposition is critical to integrated circuit manufacturing, ranging in scale from nanometer features in damascene plating to micrometer scale through-silicon via structures and even millimeter scale printed circuit board fabrication. Essential to this technology is electrodeposition of void-free copper in high aspect ratio cavities, which is achieved through various additives that enable bottom-up filling. In through-silicon-via structures, void-free filling can be realized with micro-to-milli molar concentrations of polyether suppressor and chloride additives. A variety of analytical measurements have shown chloride adsorption on copper is a necessary precursor to formation of a polyether blocking layer to suppress deposition. In this study, experimental measurements and computational models are presented exploring the dynamics of polyether and chloride adsorption during copper deposition. Microelectrode measurements eliminate solution iR effects, while demonstrating comparable results to rotating disk electrode systems at equivalent transport conditions. A two-additive co-adsorption model for polyether and chloride is presented, comparing simulations to experimental feature filling at conditions when chloride transport is limiting formation of the inhibiting ad-layer (< 80 μmol/L). Suppression breakdown is related to the local polyether coverage, which is in turn limited by the chloride coverage on the depositing interface. A passive-active transition of copper deposition is associated with limited flux of chloride in the feature. At higher chloride concentrations (≥ 80 μmol/L), sidewall breakdown during deposition occurs nearer to the bottom of the via, followed by a shift to bottom-up growth.