The rapid increase of devices with artificial intelligence (AI) and machine learning capabilities is driving the demand for growth in compute performance. With transistor scaling reaching physical limitations, the semiconductor industry is looking to system-scaling to deliver the performance improvements. Advanced packaging architectures capable of supporting these applications are 2.5D interposers, 3D IC stacking, chiplets and fan-out based packaging. All of these architectures require high-density interconnects capable of routing >200 IOs/mm/layer. This talk demonstrates advanced ultra-thin ( <10 µm), low-D_k (< 3.0) polymer dielectric material candidates capable of achieving I/O densities of 500 IOs/mm/layer.

Current commercially available solutions based on silicon interposers suffer from conductor and dielectric losses because of restrictions on the dielectric material (SiO₂). Polymer based dielectrics offer a compelling alternative because of the potential to reduce the capacitance of the traces and improve power efficiency alongside compatibility with low-cost panel-scalable processes. This idea is explored will be explored in this talk and we will demonstrate through modelling and characterization that low-D_k polymer dielectrics are a superior candidate to current dielectric material candidates

The choice of polymer dielectric is driven by technology trends towards a)high-density fine-pitch routing b)system level thermo-mechanical reliability c)panel-scalable processing. This work examines four dielectric material candidates comprising of 3 material classes, namely photo-sensitive epoxy, non-photo-sensitive epoxy and BCB for next-generation interconnect technology. High-speed electrical simulations indicate that low-D_k materials can support data rates of >10Gbps which overcomes the limitations faced by conventional high D_k epoxy dielectrics and SiO₂ alternatives.

The biggest challenge in moving towards low-D_k materials is that these polymers are typically non-polar and do not adhere well which poses challenges in package integration. This work proposes a unique approach to improve polymer/metal interfacial adhesion by creating a hybrid layer with tailorable material properties using vapor-phase-infiltration (VPI). VPI exposes the polymeric material to a metal-organic reactant such as trimethyl aluminium (TMA) in a heated environment. Diffusional kinetics of the reactant are highly dependent on each step of the sequential process such as temperature, time of hold, exposure time, and co-reactants used. This process is superior compared to Atomic Layer deposition (ALD) in promoting the diffusion of organometallic precursors into the polymer subsurface because of a hold-period after exposure. VPI thereby provides a highly adaptable process to create tunable hybrid interfaces with target properties. VPI-treated polymers showed a 3X improvement in adhesion strength at the polymer/metal interface. This work dives into the kinetic factors required to achieve this adhesion improvement and characterizes the corresponding material structure changes.

In summary, advanced low-D_k polymer dielectrics capable of meeting next-generation high-performance computing requirements are discussed. This work evaluates the key performance benefits from moving to low-D_k dielectric materials and tackles a critical challenge of integrating these materials as re-distribution layer (RDL) dielectrics by demonstrating 3X improvement in adhesion using VPI.