G06 - 2.5 and 3D Packaging

Wednesday, 16 October 2019: 10:00-12:00
Room 210 (The Hilton Atlanta)
Chairs:
Makoto Motoyoshi and Lingyun Wei
10:00
(Invited) CdTe/Si-Roic Staced X-Ray Imaging Sensor
T. Aoki (Shizuoka University, ANSeeN Inc.), K. Takagi (ANSeeN Inc., Shizuoka University), T. Takagi (Shizuoka University), H. Kase (Shizuoka University, ANSeeN Inc.), and A. Koike (ANSeeN Inc., Shizuoka University)
10:40
(Invited) Application of Three Dimensional Chip Stacking Technology for Fully Depleted Silicon-on-Insulator Quantum Beam Imager
I. Kurachi, T. Tsuboyama, Y. Arai (High Energy Accelerator Research Organization (KEK)), and M. Motoyoshi (Tohoku-MicroTec Co., Ltd)
11:20
Advanced Low-K Polymer Dielectric Materials and Interfaces for Fine-Pitch Re-Distribution-Layer (RDL) to Enable 2.5D and Fan-out Packages
S. Dwarakanath (Georgia Institute of Technology), P. M. Raj (Florida International University), M. D. Losego, and R. R. Tummala (Georgia Institute of Technology)
11:40
Low-Dielectric Constant Nanoporous Epoxy for Electronic Packaging
J. Jiang, L. Keller, and P. A. Kohl (Georgia Institute of Technology)
See more of: G06: Materials and Processes for Semiconductor, 2.5 and 3D Chip Packaging, and High Density Interconnection PCB 2
See more of: Electronic Materials and Processing
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