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(Digital Presentation) Characterization and Compression Technology of 3D Corner Residue between Dummy Gate and Fin during an Advanced Inductive Coupled Plasma Gate Etch Process in FinFET

Tuesday, 31 May 2022: 11:20
West Meeting Room 115 (Vancouver Convention Center)
X. Xiao (Semiconductor Manufacturing International Corporation), Y. Wang (Semiconductor Manufacturing International Corp.), B. Su (Semiconductor International Manufacturing Corp.), X. Ke, S. Ji (Semiconductor Manufacturing International Corporation), and H. Y. Zhang (Semiconductor Manufacturing International (Shanghai) Corporation)
3-Dimesional corner residue between Fin and gate bottom plays a key role in gate profile definition and device performance, while the characterization and compression remain challenging due to shortage of analysis technology and decreasing gate/Fin pitch. In this work, cross-section and planar TEM/STEM are adopted together to measure the real corner size. Gate profile loading along Fin is discussed based on the characterizations and further optimized by tuning processes. Several methods including sidewall passivation and ion bombardment modification has been introduced. An excellent FinFET performance is presented, together with a detailed mechanism.

See more of: G02 - Advanced Semiconductor Materials, Devices and Processing 2
See more of: G02: Silicon Compatible Emerging Materials, Processes, and Technologies for Advanced CMOS and Post-CMOS Applications 12
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