Low temperature Area-Selective Deposition (ASD) is becoming an important need in semiconductor manufacturing to augment photolithography for improved resolution and alignment of printed features. Area-selective deposition is used routinely at temperature in excess of 800°C to form epitaxial transistor contacts, but for back-end applications, new ASD processes are needed that work at <400°C. This tutorial will introduce the challenges of low temperature ASD, and summarize recent advances in this field, including ASD via Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD), and understanding of feature size dependence and lateral “mushroom” growth. We will review approaches using surface passivation, including self-assembled monolayers and small molecule inhibitors, as well as approaches based on inherent differences in nucleation on different clean surfaces. Further, we will present emerging approaches that achieve patterning by taking advantage of native selectivity in nucleation and etching reactions, for example, where ALD and Atomic Layer Etching (ALE) can be combined, either in sequence or in parallel, to achieve desired outcomes. We will also review current modeling efforts, including methods to quantitatively analyze ASD and compare results for different materials and different processes, highlighting the challenges of understanding reactions for initial nucleation and nucleus removal.