Heavily-doped Si is of great importance for source/drain (S/D) applications in advanced node devices. Arsenic (As) is a typical n-type dopant in Si that is being investigated because of its smaller thermal diffusion length than that of phosphorous. Thus, using As has an advantage close to the channel of the device where one needs to control dopant’s diffusion [1]. UV laser annealing (UV-LA) has the capability of forming ultra-shallow junctions since the short penetration length of UV light in Si leads to surface-localized heating. In addition, LA enables metastable activation of dopants beyond the solid solubility limit [2]. These potential advantages of using UV-LA attract increased attention from the semiconductor industry, especially for 3D-integrated device manufacturing [3]. However, activation control and placement of dopant atoms becomes complex when the doping level is increased to very high levels. For instance, excess doping concentration may introduce stacking faults during the regrowth because of a possible failure of placing atoms in the crystalline network. Additionally, high dopant density also may lead to increased dopant clustering, which has been known to reduce net activation. Understanding the electrical impact of laser-annealing on highly doped Si requires the measurement of carriers and mobility at high enough resolution through the near-surface region.

Differential Hall effect metrology (DHEM) provides depth profiles of mobility, resistivity, and carrier concentration through a semiconductor thin film. DHEM depth resolution can be sub-nm and so can effectively be used to understand the electrical impact of the above mentioned crystallographic defects. In this contribution, we investigated it by means of the highly active Si layer realized by UV-LA and various physical analyses.

In a DHEM measurement, an electrically isolated cross-shaped Van der Pauw test-pattern is prepared on the sample to be characterized. Four electrical contacts are formed at the ends of the four arms of the test-pattern and a nozzle is sealed against a process area that includes a test region at the center of the test-pattern, where the four cross arms meet. The nozzle has the capability of delivering an electrolyte to the surface of the process region. Through electrochemical oxidation the electrically active thickness of the layer at the test region is reduced stepwise manner and measurements of R s and Hall voltage are carried out after each thickness reduction step. Each successive measurement is a Van der Pauw/Hall Effect measurement. Data collected can then be processed to yield depth profiles of resistivity, mobility, and carrier concentration.

The 70-nm-thick SOI wafer was implanted with As and then submitted to UV-LA with the stage at room temperature under nitrogen. The applied UV-LA condition resulted in the monocrystalline regrowth of the amorphized layer.

XTEM (Fig. 1) shows stacking faults and black non-uniform contrast possibly implying the presence of defects near the regrown Si surface. Interestingly, DHEM mobility profile also shows a drop (>50%) in the same region. A further investigation (e.g., residual strain in the regrown Si layer) will be conducted and presented in the conference.

References

1. 1. Rosseel, C. Porret, A. Hikavyy, R. Loo, M. Tirrito, B. Douhard, O. Richard, N. Horiguchi and R. Khazaka, ECS Transactions, 98(5), 37-42 (2020).
2. A. Lietoila, J. F. Gibbons and T. W. Sigmon, Appl. Phys. Lett., 36, 765-768 (1980).
3. A. Vandooren et al., 2020 IEEE Symposium on VLSI Technology, TH3.2.