Introduction

Ultrathin body (UTB) Ge-on-insulator (GeOI) is compulsory structure for improved gate control and immunity against short channel effects in the ultimately scaled high performance and low power CMOS. However, severe carrier mobility degradation has been reported in commercially available Smart-Cut^TM GeOI substrates with body thickness (T_body) less than 20 nm [1, 2]. Unstable Ge/buried oxide (BOX) interfaces, poor Ge crystallinity and Ge thickness fluctuation are main obstacles in conventional UTB GeOI structures. Therefore, more sophisticated fabrication methods are strongly required. In this work, a novel Ge layer transfer technology called HEtero-Layer-Lift-Off (HELLO) [3] utilizing SiGe etch stop layer and Si passivation layer in the donor structure has been developed for precise control of T_body and back interfacial quality in UTB GeOI. Enhancement of carrier mobility in both UTB GeOI n and pMOSFETs has been demonstrated, showing high potential of UTB GeOI by HELLO technology [4, 5].

HELLO technology

The schematic flows of HELLO technology for fabricating GeOI substrates is shown in Fig. 1. As a donor structure, Ge channel (20 nm)/Si_0.3Ge_0.7 etch stop layer (6.5 nm)/Ge buffer layer (500 nm)/AlAs/GaAs hetero-structures were grown by low-pressure CVD. To improve back interfacial quality, plasma treatment or 0.5-nm-thick Si passivation on top of Ge layer prior to ALD-Al₂O₃ deposition were carried out for GeOI n or pMOSFETs, respectively. Then, the direct bonding to SiO₂/Si host substrate was performed in press machine under vacuum at 200 °C. Note that the direct bonding was performed at interface of Al₂O₃/SiO₂ to prevent the damage for Ge channel layer. To release GaAs substrate, the AlAs layer was etched selectively and laterally in HCl solution at room temperature. Then, Ge buffer layer and Si_0.3Ge_0.7 etch stop layer were etched, sequentially. This HELLO technology was performed at low temperature to avoid thermal stress, leading to high quality GeOI structure. The detailed fabrication method for GeOI MOSFETs can be found elsewhere [4].

GeOI n and pMOSFETs

Figures 2 show the I_D-V_G transfer chcaracteristics of UTB GeOI n and pMOSFETs fabricated with HELLO technology with T_body of 3 and 4 nm, respectively. Comparable device performance has been achieved and a high I_on-I_off ratio of 10⁵ has been obtained in both devices. The TEM image of ultrathin GeOI channel (3 nm) in MOSFETs fabricated through HELLO technology is also shown in the inset. Single crystalline Ge layer with precise channel thickness control down to 3 nm was achieved. Positive V_th shift was observed in GeOI pMOSFETs as compared with that of nMOSFETs, which can be attributed to carrier confinement at Si-passivated GeOI back interface owing to Ge/Si valence band offset. Figures 3 show the benchmarks of T_body dependence of effective (a) electron and (b) hole mobility at N_S of 2×10¹² cm^-2. The mobility of reported GeOI [1, 2] and SOI devices [6] are also plotted for comparison. Severe mobility degradation with scaling T_body was found for both n and pMOSFETs as fabricated with conventional GeOI substrates. Nevertheless, it was confirmed the effective electron mobility in HELLO fabricated GeOI significantly increased with scaling T_body below 10 nm. This unique phenomenon may be attributed to the modulation of Ge conduction band structure [4]. On the other hand, GeOI pMOSFETs attained much higher mobility of about 150 cm²/Vs in UTB regime. The trend of mobility degradation with scaling T_body was also suppressed for the devices fabricated with HELLO technology, presenting the clear benefit of reducing thickness fluctuation and Si-passivated back interface. Thanks to HELLO technology, for the first time, GeOI n and pMOSFETs both outperformed their SOI counterparts in UTB regime.

Conclusion

High quality GeOI substrates have been successfully fabricated through HELLO technology. Both electron and hole mobility in GeOI devices outperformed their SOI counterparts in UTB regime, indicating that UTB-GeOI structure is very promising for future Ge CMOS applications.

Acknowledgement

The authors would like to thank the support from Sumitomo Chemical Co., Ltd. and Hitachi Kokusai Electric Inc. for Ge layer transfer technology and AIST-NPF for device fabrication.

References

[1] C. H. Lee et al., IEEE International SOI Conf. 1 (2011). [2] X. Yu et al., Microelectron. Eng. 147, 196 (2015). [3] T. Maeda et al., Appl. Phys. Lett. 109, 262104 (2016). [4] W. H. Chang et al., IEEE Trans. Electron Device 64, 4615 (2017). [5] W. H. Chang et al., Appl. Phys. Exp. 9, 091302 (2016). [6] K. Uchida et al., IEDM 47 (2002).