In the last forty years, complementary metal oxide semiconductor (CMOS) technology has made tremendous progress and its advancement has enabled physical scaling of CMOS electronics technology. Physical scaling has offered us higher data processing performance but with the increased penalty of power consumption. As we approach physical scaling, alternative materials, device architecture, physics and integration strategies have been proposed to overcome this fundamental physical roadblock. This problem specially exaggerates for implantable and bioelectronics where we need higher data performance but at the same time lower power consumption. Specially body integration restricts heat dissipation related power consumption to 40 mW/cm². Therefore, we have conceptualized a newly minted nanotube architecture with the classical crystalline material such as silicon (Si), Silicon-Germanium (SiGe), Germanium (Ge), III-V materials and applying tunnel physics we have developed an integration strategy where a core-shell gate stacks in a coin like configuration (sensors on sensing surface connected via through-polymer-via (TPV) to homo and heterogeneous crystalline materials based nanotube tunnel FETs with core-shell gate stacks on the other side for higher information processing performance and lower power consumption. In this talk, we will discuss this novel device architecture, its physics, choice of materials and integration strategy specially for brain-machine interfacing.