Germanium (Ge) has been intensively investigated as a high-mobility channel material alternative to silicon (Si). A high quality Ge/dielectric interface with interface state density D_it compared to Si is required for competitive device performance. GeO₂ has been identified as potential candidate for an interfacial layer (IL) due to effective Ge surface passivation with D_it in the range of 10¹¹ cm^-2eV^-1 [1]. However, in order to achieve scaled effective oxide thickness (EOT) a combination of GeO₂ IL and a high-k dielectric is needed. Low interface state density in the range of 10¹¹ cm^-2eV^-1 has been achieved while employing Al₂O₃ barrier [2] as well as rare earth oxides such as Y₂O₃ [3]. Rare-earth thulium oxide (Tm₂O₃) provides high dielectric constant k~16 [4] and sufficient valence (3.05 eV) and conduction (2.05 eV) band offsets [5] for a high-k dielectric layer on Ge. In this work Ge/GeO_x/Tm₂O₃ interface quality and the impact of post deposition anneal ambient are investigated.

Metal oxide semiconductor (MOS) capacitors were fabricated to evaluate Ge/GeO_x/Tm₂O₃ gate stacks. After n-Ge substrate clean (acetone, propanol and O₂ plasma) and native germanium oxide removal with aqueous HF and HCl solutions the samples were immediately loaded into the rapid thermal anneal (RTA) chamber where oxidation was carried out at 550 °C for 5 s to 5 min. The temperature in the chamber is controlled by a pyrometer which is calibrated to a Si wafer, and oxidation is performed by placing a Ge substrate piece on a Si carrier wafer. The temperature of the Ge sample is thus lower than that of the Si wafer. After oxidation the samples were loaded to atomic layer deposition (ALD) chamber where 40 cycles (~7 nm) of Tm₂O₃ were deposited using TmCp₃ and H₂O as precursors. Then Ge/GeO₂/Tm₂O₃ gate stacks were annealed in different ambient (O₂, O₃, N₂ and H₂/N₂) and temperatures (400 - 550 °C). Reference samples without Tm₂O₃ deposition or without post deposition anneal (PDA) were also fabricated. Al gate metal was deposited by physical vapor deposition and patterned. MOS capacitors were electrically characterized with capacitance-voltage (CV) measurements. Interface state density in the midgap was evaluated from CV curves using a method described in [6]. X-ray photoelectron spectroscopy (XPS) was performed on some samples using Al Kα X-ray (1486.6 eV) source and PSP Vacuum Technology electron energy analyser.

Electrical properties of thermally grown Ge/GeO₂ interfaces were evaluated and low interface state density D_it < 5·10¹¹ cm^-2eV^-1 in the midgap was extracted from CV measurements. The influence of Tm₂O₃ deposition on high-quality Ge/GeO₂ interfaces was then determined. A degradation of the interface quality after the deposition was observed as displayed in Fig. 1. D_it is higher for thinner underlying GeO_x layer and seems to saturate to ~9·10¹¹ cm^-2eV^-1 for thick layers. A series of post deposition anneals in different ambient and temperatures were performed on Ge/GeO_x/Tm₂O₃ gate stacks in order to investigate the influence on the interface state density and capacitance equivalent thickness (CET). The results are shown in Fig. 2. It can be seen that a temperature of 500 °C or higher and O₂ ambient is needed to sufficiently reduce D_it, when values as low as 2·10¹¹ cm^-2eV^-1 can be reached. XPS measurement was performed on Ge/GeO_x/Tm₂O₃ gate stack with O₂ PDA at 500 °C and the obtained spectrum is shown in Fig. 3. The difference between the GeO_x 3d_5/2 peak and Ge⁰ 3d_5/2 peak is 2.7 eV which corresponds to Ge³⁺ oxidation state. This result is consistent with previously reported XPS results on Ge/GeO_x/Al₂O₃ stacks [7] and suggests that Ge³⁺ oxidation state provides the low D_it values of Ge/GeO_x/Tm₂O₃ gate stacks.

Tm₂O₃ integrated with GeO₂ and O₂ PDA is a viable candidate for Ge MOS devices due to low interface state density of ~2·10¹¹ cm^-2eV^-1 which is correlated to Ge³⁺ oxidation state. A further investigation of O₂ PDA time in terms of the trade-off between D_it and CET will be reported.

References

[1] H. Matsubara et al., Appl. Phys. Lett., vol. 93, no. 3, p. 32104, 2008.

[2] R. Zhang et al., IEEE Trans. Electron Devices, vol. 61, no. 2, pp. 416–422, 2014.

[3] C. H. Lee et al., Tech. Dig. - Int. Electron Devices Meet. IEDM, pp. 40–43, 2013.

[4] E. Dentoni Litta et al., J. Electrochem. Soc., vol. 160, no. 11, pp. D538–D542, 2013.

[5] I. Z. Mitrovic et al., J. Appl. Phys., 2015.

[6] L. Zurauskaite et al., EDTM, pp. 164–166, 2017.

[7] X. Wang et al., Appl. Surf. Sci., vol. 357, pp. 1857–1862, 2015.