Power electronics is currently a very active topic, with multiple academic and industrial players working on GaN based materials, in particular due to the availability of HEMT structures as shown in figure 3 that can be integrated on silicon substrates. Such structures have high carrier mobility and the capability to withstand high critical electrical fields, which makes them extremely promising for power conversion applications at lower cost compared to bulk silicon carbide devices for example. Moreover, with aggressive device scaling compared to silicon power transistors, such devices allow higher frequency operation which in combination with high temperature operation, ensure more compact and greener energy converters at more competitive prices.
Beyond traditional power conversion, radio frequency applications are also a field where GaN is of great interest. Although the market is today mainly covered by GaN on silicon carbide layers to address high performance demands such as military radar, high volume markets are now pushing for products at more competitive prices. In particular GaN on silicon is a candidate of increasing interest for the next generation of 5G networks in development.
Finally, GaN on silicon has been proposed for many years as a solution to reduce LED fabrication costs. However the move into production has not occurred on a large scale, in particular due to the ever decreasing costs of GaN on sapphire devices and the difficulties of growing the very high quality GaN required for LEDs on silicon substrates. However, new applications such as micro-displays, with pixels shown in figure 4, are once again making GaN on silicon attractive for LEDs production, as large wafers and low defectivity of CMOS compatible processing mean that pixel yield and therefore device yield can be maintained, which is much harder to achieve for traditional GaN on sapphire production.
This talk will describe the basics of growth of GaN on silicon, and the techniques of strain engineering required to produce flat wafers at room temperature. We will also look at the different in-situ characterizations available and discuss the different information that we can extract from these to ensure easier development of layers and better control of production.
We will then examine the specific challenges of GaN on silicon growth, and the difficulties associated with the integration of these layers into CMOS compatible fabs. In particular, we will look at the different forms of defectivity found during GaN on silicon growth, with an example shown in figure 5. These defects must be avoided, to ensure high performance and high yield, to ensure CMOS compatibility and also to avoid an impact on the fragility of wafers, which is a serious issue for GaN on silicon wafers. We will also present some of the current solutions being implemented by LETI in order to counteract these difficulties and move towards truly CMOS compatible layers. An example of a fully processed wafer is shown in figure 6.
Finally we will examine the specific challenges for GaN on silicon for each of the above applications, in terms of layer performance and integration difficulties, before looking ahead to future concepts for GaN on silicon layers, and further integration of these layers including hybrid LED micro-displays, and integrated circuits for power electronics.