Scaling of semiconductor devices over past decades has been made possible by continuous innovations in materials engineering as well as device geometries and integration [1,2]. Shrinking device features necessitate precise engineering of various materials and interfaces. Thermal processing plays a key role in engineering of ever-evolving materials and processes governed by thermodynamics and kinetics. High-k metal gate (HKMG) and contact to source-drain present key challenges in meeting device performance and yield requirements for continued logic CMOS scaling. In this paper, we will present equipment and process innovations in millisecond annealing that enable HKMG and source-drain contact scaling.

Key requirements for HKMG architecture include EOT scaling, device reliability, maintaining desired effective work function, and minimal Vfb roll-off effect. Thermal treatment of HKMG film stack leads to HfO₂ crystallization, reaction of HfO₂ with the SiO₂ interface layer (IL), diffusion of nitrogen (N) and reaction with HfO₂, and displacement of oxygen vacancies from HfO₂. In addition, nitridation of HfO₂ suppresses charge traps, improving reliability. Nitrogen placement in the HKMG stack is a function of annealing conditions, and needs to be controlled precisely to meet device performance and reliability requirements. HKMG integration can benefit greatly from millisecond annealing that offers high temperature processing but in millisecond time scales. In this paper, we will introduce millisecond annealing in ammonia (NH₃) ambient. We will demonstrate that millisecond annealing in NH₃ ambient offers unique capabilities in controlling the N dose and placement in the HKMG stack. It is extremely important to control the N profile since N penetration to the interface layer degrades PMOS reliability. Fig 1 shows the three film stacks investigated in this work. Millisecond annealing was performed using a scanning continuous wave laser to reach desired surface temperature of a wafer placed on a heated stage. This approach allows for millisecond scale control of thermal energy delivery to the wafer. Fig 2 shows the N concentration as a function of millisecond anneal peak temperature for different heater temperatures. N incorporation increases with peak temperature. Lower heater temperature enables higher N incorporation. As shown in Fig 3, lower heater temperature also results in lesser IL thickening, which is desirable for EOT scaling. Fig 4 shows angle-resolved X-Ray Photoelectron Spectroscopy (AR-XPS) profiles for HfO₂/IL film stack annealed at the same peak temperature but with different heater temperatures. Clearly, lower heater temperature leads to shallower, Gaussian-like N profile contained within HfO₂. In this paper, we will also demonstrate nitridation of other HKMG film stacks such as TiN/HfO₂/IL, and TaN/HfO₂/IL with excellent control over N dose and depth profile. We will show that this approach leads to conformal nitridation of HKMG film stack. We will also present MOSCAP data complementing the physical characterization and demonstrating device performance and reliability benefits of millisecond annealing in NH₃ ambient.

Continued CMOS scaling requires geometric shrinking of device features such as contact to source and drain. Smaller contact dimensions necessitate reduction of bulk and interface resistivity of various materials deposited in the contact structure. Advanced logic devices beyond 10nm node are expected to use Cobalt as contact fill metal [3]. Oxidation of barrier TiN is detrimental to the quality of subsequent Cobalt metal fill and introduces an additional contributor to the overall external resistance of the device. Silicidation anneal after Ti liner/TiN barrier deposition results in oxidation of TiN surface due to the presence of trace amounts of O₂ in the anneal chamber. Hence, it is paramount to minimize surface oxidation of TiN to enable optimal contact metal fill. In this paper, we will demonstrate that TiN oxidation can be minimized by improving millisecond anneal chamber background O₂ level and cooling down wafers in controlled ambient. The importance of ambient control during silicide anneal was investigated by comparing surface oxidation resulting from annealing with various ambient control schemes. Fig. 5 shows that a silicide anneal run with X ppm ambient O₂ during the anneal resulted in significant oxidation of TiN, and oxidation was reduced with reduced ambient O₂ during anneal. The least degree of TiN oxidation was achieved with improved ambient control during both the anneal process and wafer cooldown. Improvement in chamber O₂ level along with cooler wafer extraction also resulted in better Co adhesion to TiN and ~17% reduction in contact resistivity (Fig 6). Enhanced ambient control capability in the millisecond anneal system is expected to provide further benefits in HKMG EOT scaling and reliability in combination with NH₃ thermal processing.