Exponential growth in the number and capability of computing and communication devices over the past several decades has led to the proliferation of information technology, with transformative impact on society. Key to this rapid growth has been transistor miniaturization (“scaling”), which enables ever higher levels of integration on a silicon chip following Moore’s Law, to provide for improved integrated circuit (IC) performance and functionality per unit area. As the incremental benefits of classic (Dennard) scaling diminished due to fundamental limits for transistor operation, the industry resorted to the incorporation of the semiconductor alloy silicon-germanium (SiGe) to steadily improve the performance of complementary metal-oxide-semiconductor (CMOS) transistors and thereby enable Moore’s Law to be sustained. The application of doped polycrystalline SiGe as an alternative MOSFET gate material was first proposed and demonstrated in 1990; subsequently it was shown to provide for reduced gate depletion effect and reduced dopant penetration into the underlying gate dielectric layer, resulting in improved CMOS transistor performance and scalability as well as superior transistor reliability at deep-submicron gate lengths. The first report of using epitaxial SiGe in the source and drain regions of a metal-oxide-semiconductor field-effect transistor (MOSFET) to enhance p-channel transistor performance was in 1999. Intel Corporation was the first company to adopt this innovation in high-volume manufacturing, beginning at the 90 nm generation of CMOS technology (“node”) in 2004. The benefit of using a thin epitaxially grown layer of SiGe in the channel region to enhance the performance of sub-100 nm CMOS transistors was first demonstrated in 2000. Samsung Electronics was the first company to manufacture CMOS products with epitaxial SiGe as the (p-)channel material, beginning at the 32 nm node in 2011.

The adoption of the three-dimensional (3-D) fin-shaped MOSFET design (“FinFET”) facilitated continued transistor miniaturization to gate lengths below 25 nm, beginning at the 22 nm node in early 2012. Further transistor evolution not only to facilitate continued scaling but also to achieve high on/off current ratio with lower operating voltage for improved energy efficiency will be necessary to sustain the rapid growth of the semiconductor industry beyond the next decade. Due to lighter carrier tunneling effective mass (which results in degraded subthreshold swing) and larger dielectric permittivity (which results in greater drain-induced barrier lowering), as well as the difficulty of growing a thick/tall layer of SiGe with low defect density on a silicon wafer (the substrate of choice for high-volume chip manufacturing), nanoscale SiGe FinFET performance superior to that of state-of-the-art Si FinFETs has proven to be elusive. To overcome this challenge, we recently proposed a novel hybrid-channel FinFET design that is compatible with a conventional FinFET manufacturing process flow. 3-D device simulations indicate that the hybrid-channel design can achieve than 20% larger on-state drive current for the same operating voltage, as compared against a Si-channel design, at sub-15 nm gate length. In this paper, hybrid-channel FinFET design optimization and sensitivity to process-induced variations will be discussed, to demonstrate that SiGe can continue to be an enabler of Moore’s Law beyond the 5 nm node.