Headwinds faced by scaling efforts of high performance logic technology have forced engineering teams to go beyond dumb shrinking of device dimensions and into clever employment of new materials and structures, over last few technology nodes. We departed technology staple, planar transistors, and entered into 3D structures, half a dozen years ago. Such paradigm shifts will continue to happen more often in the years to come. We will look at today's state-of-the-art devices - FinFETs - and explore capability and suitability of new architectures for years to come. Those include variants of gate-all-around (GAA) transistors, horizontal and vertical, negative-capacitance FET (NCFET), tunnel FET (TFET), and spin-based devices. We'll assess feasibility of material contenders for better channel transport - III-V, SiGe/Ge, carbon nanotubes (CNT) and 2D transition metal di-chalcogenides (TMD). Finally, we discuss 3D monolithic device stacking and standard cell level design-technology co-optimization role in scaling.