Silicon germanium (SiGe) channels for CMOS are favorable due to high intrinsic carrier mobility and band gap tunability[1] To utilize the superior properties of SiGe, low interface defect density (Dit) must be obtained at the SiGe-high k interface. Germanium oxide (GeOx) is the primary source of interface defects[2]. In comparison with GeOx, SiOx has a higher heat of formation. Using this difference, it is possible to reduce interface defects with selective reduction or diffusion of GeOx by employing an oxygen-scavenging metal as a gate material[4,5] such as aluminum. ALD was performed with TDMAH and H₂O to grow 50 cycles (5nm) of HfO₂ at 250C. 50 nm thick, 150 um diameter Ni or Al gate metal was deposited by thermal evaporation. C-V measurement were employed to characterized the electronic defects. The interface trap density (Dit) integrated across the band gap was more than an order of magnitude lower for Al vs Ni gated MOSCAPs. From TEM-EELS-EDS measurement, Al gated MOSCAPs were observed to have a very thin interfacial oxide layer (<0.5 nm) with high-k oxide atoms almost directly bonded with the SiGe surface atoms with just a thin SiOx interlyer. Selective scavenging of Ge-O vs Si-O bonds is consistent with a DFT model showing HfO₂/SiOx/SiGe interfaces can be defect-free. DFT models also show that two 3- and 5-fold coordinated interfacial Si atoms do not create any mid-gap or band-edge states. These results indicate the need to form a SiOx interface between HfO2 and SiGe, but the same interface may be created with other techniques. The alternative techniques include a selective oxidation of SiGe form SIOx using remote O₃ oxidation and ALD of an Si rich layer on SiGe. The key issue is which of the three techniques is manufacturable and can produce both a scale oxide and scaled interlayer.

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