Over the past decade, CMOS device and integrated circuit technology has rapidly evolved toward the use of complex 3D structures that are fabricated using new materials and processes with ever decreasing dimensions. FinFET transistor is now the dominant microprocessor device architecture, and the challenges associated with its 3D nature of all measurements are amplified by shrinking dimensions. This paper reviews the device physics and key front end wafer fabrication challenges of the state-of-the-art FinFET technology. It highlights the area of metrology and characterization that is needed to enable process development, fast ramping in pilot lines and start-ups, reducing time-to-market for new products and yield improvement in mature factories