Si, SiGe and III-V Bonding

Wednesday, 3 October 2018: 08:00-10:00
Universal 14 (Expo Center)
Chairs:
Karl D. Hobart and Maik Wiemer
08:00
967
(Invited) Monolithic Integration of Si-CMOS and III-V-on-Si through Direct Wafer Bonding Process
K. H. Lee, L. Zhang, B. Wang, Y. Wang, W. Sasangka, K. E. Lee (SMART Low Energy Electronic Systems), and E. A. Fitzgerald (SMART Low Energy Electronic Systems, Massachusetts Institute of Technology)
08:40
968
Atomistic Structure of Low-Resistance Si/GaAs Heterointerfaces Fabricated By Surface-Activated Bonding at Room Temperature
Y. Ohno (IMR, Tohoku University), H. Yoshida, S. Takeda (ISIR, Osaka University), J. Liang, and N. Shigekawa (Osaka City University)
09:00
969
The Role of Misorientation in Direct Wafer Bonded III-V Materials
M. Liao, V. Tran, M. Yee, M. Seal (University of California, Los Angeles), and M. S. Goorsky (University of California Los Angeles)
09:20
970
Si-Ge Heterostructures Fabricated by Room Temperature Wafer Bonding
N. Razek (EV Group, G-Ray Industries SA), V. Dragoi (EV Group), A. Jung, and H. von Känel (Empa, Switzerland)
09:40
971
Room Temperature Bonding of Wafers Using Si and Ge Films with Extremely Low Electrical Conductivity
M. Uomoto, A. Muraoka (FRIS, Tohoku University), and T. Shimatsu (RIEC, Tohoku University, FRIS, Tohoku University)
See more of: G01: Semiconductor Wafer Bonding: Science, Technology, and Applications 15
See more of: Electronic Materials and Processing
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