Si Channel: Gate Stack Reliability

Tuesday, May 14, 2013: 14:00-15:40
Norfolk, Mezzanine Level (Sheraton)
Chairs:
E. P. Gusev and P. J. Timans
14:00
868
(Invited) Metal Gate/High-κ Dielectric Gate Stack Reliability; or How I Learned to Live with Trappy Oxides
Barry P. Linder, Ph.D., IBM Corporation; Eduard A. Cartier, IBM T.J. Watson Research Center; Siddarth Krishnan, IBM Corporation
14:40
869
Impact of Lanthanum on Positive-Bias Temperature Instability – Insight from First-Principles Simulation
Chenjie Gu, PhD Candidate, Nanyang Technological University; Diing Shenp Ang, PhD, Nanyang Technological University
15:00
Break
15:20
870
On the Evolution of Switching Oxide Traps in the HfO2/TiN Gate Stack Subjected to Positive- and Negative-Bias Temperature Stressing
Yuan Gao, Nanyang Technological University; Diing Shenp Ang, Ph.D., Nanyang Technological University; Chen Jie Gu, Nanyang Technological University
See more of: E5: Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3
See more of: Dielectric and Semiconductor Materials, Devices, and Processing
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