E5 Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3

Lead Organizer: F. Roozeboom (University of Technology)

Co-organizers: E. P. Gusev (Qualcomm MEMS Technologies) , Hiroshi Iwai (Tokyo University of Technology) , Kuniyuki Kakushima (Tokyo Institute of Technology) , D.-L. Kwong (Institute of Microelectronics) , Vijay Narayanan (IBM T.J. Watson Research Center) and P. J. Timans (Mattson Technology Inc.)

Monday, May 13, 2013

08:35-10:00


Welcome & Plenary Session
F. Roozeboom, E. P. Gusev, Hiroshi Iwai, Kuniyuki Kakushima, D.-L. Kwong, Vijay Narayanan and P. J. Timans

10:00-12:00


Planar Si &SiGe: Stressors/Gate Stack
Kuniyuki Kakushima and Vijay Narayanan

13:20-16:20


High Mobility Channels
Kuniyuki Kakushima and Vijay Narayanan

Tuesday, May 14, 2013

08:00-10:20


Non-Planar Devices: FINFETS/Nanowires
P. J. Timans and E. P. Gusev

10:20-11:40


Patterning and Lithography Challenges Part 1
Hiroshi Iwai and F. Roozeboom

13:20-14:00


Patterning and Lithography Challenges Part 2
Hiroshi Iwai and F. Roozeboom

14:00-15:40


Si Channel: Gate Stack Reliability
E. P. Gusev and P. J. Timans

15:40-20:00


3D Integration/ReRAM/MEMS
D.-L. Kwong and F. Roozeboom