Patterning and Lithography Challenges Part 1

Tuesday, May 14, 2013: 10:20-11:40
Norfolk, Mezzanine Level (Sheraton)
Chairs:
Hiroshi Iwai and F. Roozeboom
 
863
FinFET Patterning Process Challenges (Cancelled)
11:00
864
A Study of Polysilicon Gate Etch Uniformity in 300 mm Silicon Wafers
Wai Shing Lau, PhD, Nanyang Technological University-Retired; Peizhen Yang, PhD, GLOBALFOUNDRIES; Soh Yun Siah, PhD, GLOBALFOUNDRIES
11:20
865
Visualization of Plasma Etching Damage of Si Using Room Temperature Spectroscopic Photoluminescence
Shiu-Ko Jang Jian, Ph.D., Taiwan Semiconductor Manufacturing Company; Chih-Cherng Jeng, Ph.D., Taiwan Semiconductor Manufacturing Company; Ting-Chun Wang, Ph.D., Taiwan Semiconductor Manufacturing Company; Chih-Mu Huang, Ph.D., Taiwan Semiconductor Manufacturing Company; Ying-Lang Wang, Ph.D., Taiwan Semiconductor Manufacturing Company; Woo Sik Yoo, Ph. D., WaferMasters, Inc.
See more of: E5: Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3
See more of: Dielectric and Semiconductor Materials, Devices, and Processing
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