Planar Si &SiGe: Stressors/Gate Stack

Monday, May 13, 2013: 10:00-12:00
Norfolk, Mezzanine Level (Sheraton)
Chairs:
Kuniyuki Kakushima and Vijay Narayanan
10:00
849
(Invited) The Past, Present and Future of High-k/Metal Gates
Kisik Choi, GLOBALFOUNDRIES; Takashi Ando, IBM T.J. Watson Research Center; Eduard A. Cartier, IBM T.J. Watson Research Center; Andreas Kerber, GLOBALFOUNDRIES at IBM; Vamsi Paruchuri, IBM Albany NanoTech Center; John Iacoponi, GLOBALFOUNDRIES; Vijay Narayanan, IBM T.J. Watson Research Center
10:40
850
Investigation of Embedded SiGe Source/Drain for 28nm HKMG PFET Performance Enhancement
El Mehdi Bazizi, GLOBALFOUNDRIES; Alban Zaka, GLOBALFOUNDRIES; Gabriela Dilliway, GLOBALFOUNDRIES; Bo Bai, GLOBALFOUNDRIES; Maciej Wiatr, GLOBALFOUNDRIES; Francis Benistant, GLOBALFOUNDRIES; Manfred Horstmann, GLOBALFOUNDRIES
11:00
851
Si-Passivation of Epitaxial SiGe: Kinetics and Impact on Morphology
Birgit Seiss, STMicroelectronics; Didier Dutartre, STMicroelectronics
11:20
852
Very Low Electron Density in Undoped Enhancement-Mode Si/SiGe Two-Dimensional Electron Gases with Thin SiGe Cap Layers
Chiao-Ti Huang, Princeton University; Jiun-Yun Li, Princeton University; James C. Sturm, Princeton University
11:40
853
Evaluation of Stress Induced by Plasma Assisted ALD SiN Film
Kohki Nagata, Master, Meiji University; Masaya Nagasaka, Bachelor, Meiji University; Takuya Yamaguchi, Bachelor, Meiji University; Atsushi Ogura, Meiji University; Hiroshi Oji, Japan Synchrotron Radiation Research Institute; Jin-Young Son, Japan Synchrotron Radiation Research Institute; Ichiro Hirosawa, Japan Synchrotron Radiation Research Institute; Y. Watanabe, Tokyo Electron, Ltd.; Y. Hirota, Tokyo Electron, Ltd.
See more of: E5: Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3
See more of: Dielectric and Semiconductor Materials, Devices, and Processing
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